Ting Lu Phones & Addresses
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Austin, TX
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Dallas, TX
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9510 Sandstone St, Houston, TX 77036 (713) 777-9015
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San Francisco, CA
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New Rochelle, NY
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Forest Hills, NY
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New York, NY
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Green Road, KY
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San Antonio, TX
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Galveston, TX
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6817 Finklea Cv, Austin, TX 78730
Work
Company:
Avenue magazine Feb 2013
Position:
Art director assistant
Education
School / High School:
Pace University- New York, NY 2011
Specialities:
Master of Science in Publishing
Skills
Knowledge of DSR Photography • stock agencies • Digital Manipulation Expert in Adobe Ph... • InDesign • Illustrator Video Production Final Cut... • HTML5 • JavaScript Proficiency in Word • Excel • Publisher • and PowerPoint
Ranks
Licence:
New York - Currently registered
Date:
2013
Resumes
Resumes
Location:
Elmhurst, NY
Industry:
Textiles
Work:
Bradlee International
Production Assistant Intern
Oriental Guardian Jul 2010 - Dec 2010
Intern, Advertising Department 3
Chi Xun Human Resources Oct 2009 - Mar 2010
Office Assitant, Part-Time
Production Assistant Intern
Oriental Guardian Jul 2010 - Dec 2010
Intern, Advertising Department 3
Chi Xun Human Resources Oct 2009 - Mar 2010
Office Assitant, Part-Time
Education:
University of Detroit Mercy 2011 - 2012
Masters, Financial Economics Nanjing University 2007 - 2011
Bachelors, Advertising
Masters, Financial Economics Nanjing University 2007 - 2011
Bachelors, Advertising
Location:
Austin, TX
Industry:
Consumer Electronics
Work:
Intel Corporation
Intel, Chief Chip Security Architect, Principal Engineer
Stec, Inc. Aug 2012 - Aug 2013
Senior Principal Asic Architect
Xilinx Jan 2008 - Aug 2012
Principal Soc Architect
Conexant 2004 - Jan 2008
Principal Engineer
Quvis 2001 - 2004
Asic Team Leader
Intel, Chief Chip Security Architect, Principal Engineer
Stec, Inc. Aug 2012 - Aug 2013
Senior Principal Asic Architect
Xilinx Jan 2008 - Aug 2012
Principal Soc Architect
Conexant 2004 - Jan 2008
Principal Engineer
Quvis 2001 - 2004
Asic Team Leader
Education:
The Johns Hopkins University 1997 - 2000
Zhejiang University 1988 - 1992
The University of New Mexico
Masters, Electronics Engineering Xi'an Middle School
Zhejiang University 1988 - 1992
The University of New Mexico
Masters, Electronics Engineering Xi'an Middle School
Skills:
Soc
Asic
Arm
Embedded Systems
Xilinx
Fpga
Semiconductors
Processors
Ic
Microprocessors
Verilog
Rtl Design
System Architecture
Hardware Design
Tcl
Embedded Software
Firmware
Algorithms
Vhdl
Device Drivers
Digital Design
Ethernet
Systemverilog
Rtos
Microcontrollers
C
Assembly
Perl
Linux Kernel
Linux
Dsp
Wireless
Asic
Arm
Embedded Systems
Xilinx
Fpga
Semiconductors
Processors
Ic
Microprocessors
Verilog
Rtl Design
System Architecture
Hardware Design
Tcl
Embedded Software
Firmware
Algorithms
Vhdl
Device Drivers
Digital Design
Ethernet
Systemverilog
Rtos
Microcontrollers
C
Assembly
Perl
Linux Kernel
Linux
Dsp
Wireless
Work:
Avenue Magazine
Feb 2013 to Feb 2013
Art Director Assistant
Boston Area Real Estate
Boston, MA
Jun 2012 to Jun 2012
Web Designer
Mod Textiles & Perfumes Inc
2010 to Jan 2010
Project Designer
NYU Tutoring Center
New York, NY
Sep 2007 to May 2008
Officer
Feb 2013 to Feb 2013
Art Director Assistant
Boston Area Real Estate
Boston, MA
Jun 2012 to Jun 2012
Web Designer
Mod Textiles & Perfumes Inc
2010 to Jan 2010
Project Designer
NYU Tutoring Center
New York, NY
Sep 2007 to May 2008
Officer
Education:
Pace University
New York, NY
2011 to 2013
Master of Science in Publishing
New York University
New York, NY
2007 to 2011
BS in Digital Media
New York, NY
2011 to 2013
Master of Science in Publishing
New York University
New York, NY
2007 to 2011
BS in Digital Media
Skills:
Knowledge of DSR Photography, stock agencies, Digital Manipulation Expert in Adobe Photoshop, InDesign, Illustrator Video Production Final Cut Pro 3D Animation - Maya Studio Experience with Adobe Digital Publishing Suite or design for tablet Expert in Web coding CSS, HTML5, JavaScript Proficiency in Word, Excel, Publisher, and PowerPoint
Business Records
Name / Title
Company / Classification
Phones & Addresses
President
CHINA SUNERGY (US) CLEAN TECH INC
Mfg Semiconductors/Related Devices · Repair Services
Mfg Semiconductors/Related Devices · Repair Services
21 Diaz Ave, San Francisco, CA 94132
575 Market St, San Francisco, CA 94105
50 Fremont St, San Francisco, CA 94105
575 Market St, San Francisco, CA 94105
50 Fremont St, San Francisco, CA 94105
Publications
Us Patents
US Patent:
8161212, Apr 17, 2012
Filed:
Sep 22, 2010
Appl. No.:
12/888333
Inventors:
Ting Lu - Austin TX, US
Kam-Wing Li - Cupertino CA, US
Bradley L. Taylor - Santa Cruz CA, US
Kam-Wing Li - Cupertino CA, US
Bradley L. Taylor - Santa Cruz CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 13/12
G06F 3/00
G06F 1/12
G06F 3/00
G06F 1/12
US Classification:
710 71, 710 20, 710 33, 710 36, 713400, 713500, 713600
Abstract:
An embodiment of a system for implementing parallel usage of a plurality of non-volatile input/output (I/O) devices can include an interface configured to receive, from a source, a source request and a first memory coupled to the interface. The first memory can be configured to store a data unit specified by the source request. The system can include an I/O device controller coupled to the interface. The I/O device controller can be configured to correlate the source request with a plurality of I/O device requests and initiate sending of the plurality of I/O device requests to the plurality of non-volatile I/O devices in parallel. The system also can include a decoder coupled to the first memory and the I/O device controller. The decoder can be configured to receive data from the plurality of non-volatile I/O devices in parallel.
US Patent:
8248883, Aug 21, 2012
Filed:
Aug 31, 2010
Appl. No.:
12/873041
Inventors:
Ting Lu - Austin TX, US
Kam-Wing Li - Cupertino CA, US
Anatoly Belkin - Glenview IL, US
Ahmad R. Ansari - San Jose CA, US
Kam-Wing Li - Cupertino CA, US
Anatoly Belkin - Glenview IL, US
Ahmad R. Ansari - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 8/00
US Classification:
36523006, 36523001
Abstract:
A system for implementing a non-volatile input/output (I/O) device based memory can include an interface configured to receive a processor request specifying a data unit. The data unit can be specified by a processor address. The system can include an address-data converter coupled to the interface. The address-data converter can be configured to correlate the processor address of the data unit to a data block within the non-volatile I/O device. The system further can include an I/O controller coupled to the address-data converter. The I/O controller can be configured to issue a non-volatile I/O device command specifying the data block to the non-volatile I/O device.
US Patent:
8443129, May 14, 2013
Filed:
Jul 21, 2010
Appl. No.:
12/841013
Inventors:
James J. Murray - Los Gatos CA, US
Ting Lu - Austin TX, US
Ting Lu - Austin TX, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 13/12
US Classification:
710307, 710 66
Abstract:
A data bus interface channel controller circuit for an N-bit data bus is described. A FIFO command queue is coupled to receive and buffer one or more commands formatted for M-bit transactions. A FIFO data queue is coupled to receive and buffer N-bit formatted data packets. A first translation circuit is coupled to the FIFO command queue and configured to translate the each commands into a selected one of a plurality of transaction formats. A transmission control circuit is coupled and configured to receive and transmit commands removed from the FIFO command queue. The transmission control circuit is configured to track a number of outstanding transmitted commands and, in response to receiving a command having a transaction format different from the previously received command, delay transmission of commands on the N-bit data bus until the number of outstanding transmitted commands equals zero.
US Patent:
8595561, Nov 26, 2013
Filed:
Oct 27, 2010
Appl. No.:
12/913713
Inventors:
Ting Lu - Austin TX, US
Robert L. Pelt - San Jose CA, US
Bradley L. Taylor - Santa Cruz CA, US
Robert L. Pelt - San Jose CA, US
Bradley L. Taylor - Santa Cruz CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 11/00
US Classification:
714 45, 714 25
Abstract:
A method of debugging within an integrated circuit (IC) that includes an embedded processor can include detecting an event within a circuit of the IC that is external to the processor and, responsive to detecting the event, initiating a debug function within the processor. Similarly, responsive to detecting an event within the processor, a debug function within a circuit block of the IC that is external to the processor can be initiated. Trace data generated within the processor and trace data generated within the programmable fabric further can be merged to generate combined trace data.
US Patent:
8612789, Dec 17, 2013
Filed:
Jan 13, 2011
Appl. No.:
13/005994
Inventors:
Bradley L. Taylor - Santa Cruz CA, US
Ting Lu - Austin TX, US
William E. Allaire - West Chester PA, US
Hassan K. Bazargan - Saratoga CA, US
Hy V. Nguyen - San Jose CA, US
Shashank Bhonge - Bangalore, IN
Ting Lu - Austin TX, US
William E. Allaire - West Chester PA, US
Hassan K. Bazargan - Saratoga CA, US
Hy V. Nguyen - San Jose CA, US
Shashank Bhonge - Bangalore, IN
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 1/26
US Classification:
713324
Abstract:
An integrated circuit can include a processor system configured to execute program code, wherein the processor system is hard-wired. The IC also can include programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system and can be configured to implement a power off procedure under the control of the processor system.
US Patent:
20120185674, Jul 19, 2012
Filed:
Jan 13, 2011
Appl. No.:
13/005962
Inventors:
Bradley L. Taylor - Santa Cruz CA, US
Ting Lu - Austin TX, US
Ting Lu - Austin TX, US
Assignee:
XILINX, INC. - San Jose CA
International Classification:
G06F 15/76
G06F 9/30
G06F 9/30
US Classification:
712 37, 712E09016
Abstract:
A method of extending a processor system within an integrated circuit (IC) can include executing program code within the processor system implemented within the IC, wherein the IC includes a programmable fabric. The processor system further can be coupled to the programmable fabric. A process can be performed using a process-specific circuit implemented within the programmable fabric in lieu of using the processor system. A result of the process from the process-specific circuit can be made available to the processor system.
US Patent:
20120221833, Aug 30, 2012
Filed:
Feb 28, 2011
Appl. No.:
13/037234
Inventors:
William E. Allaire - West Chester PA, US
Bradley L. Taylor - Santa Cruz CA, US
Ting Lu - Austin TX, US
Sandeep Dutta - Foster City CA, US
Patrick J. Crotty - San Jose CA, US
Hassan K. Bazargan - Saratoga CA, US
Hy V. Nguyen - San Jose CA, US
Shashank Bhonge - Bangalore, IN
Bradley L. Taylor - Santa Cruz CA, US
Ting Lu - Austin TX, US
Sandeep Dutta - Foster City CA, US
Patrick J. Crotty - San Jose CA, US
Hassan K. Bazargan - Saratoga CA, US
Hy V. Nguyen - San Jose CA, US
Shashank Bhonge - Bangalore, IN
Assignee:
XILINX, INC. - San Jose CA
International Classification:
G06F 15/76
G06F 9/06
G06F 9/06
US Classification:
712 37, 712E09003
Abstract:
An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.
US Patent:
7958414, Jun 7, 2011
Filed:
Sep 22, 2010
Appl. No.:
12/888317
Inventors:
Ahmad R. Ansari - San Jose CA, US
Ting Lu - Austin TX, US
Ismed D. Hartanto - Castro Valley CA, US
Ting Lu - Austin TX, US
Ismed D. Hartanto - Castro Valley CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G01R 31/28
G11C 29/00
G11C 7/00
H03K 19/00
G06F 7/38
G11C 29/00
G11C 7/00
H03K 19/00
G06F 7/38
US Classification:
714718, 714719, 714725, 365201, 365222, 326 8, 326 39
Abstract:
An embodiment of a method of enhancing security of internal memory is disclosed. For this embodiment of the method, the application specific block is operated in a functional mode, and a reset of the application specific block is initiated. From a built-in self-test engine, at least one write to the internal memory is initiated in response to the reset initiated, where the at least one write overwrites data stored in the internal memory during a reset mode.