Cam Tan Lu

7444560, Oct 28, 2008

Oct 28, 2004

10/975315

Thai M. Nguyen - San Jose CA, US
William Shen - San Jose CA, US
Cam Lu - Milpitas CA, US

LSI Corporation - Milpitas CA

G11C 29/00
G11C 7/00
G01R 31/28

714718, 714731, 714744, 365201

A test clocking scheme that separates the clock driving the functional logic and the memory from the clock driving the test logic and the memory. In other words, the test clocking scheme separates the memory functional clock from the memory test clock into two clock paths. The test clocking scheme provides for the ability to separately shut off either the memory functional clock source or the memory test clock source, provides that less power is required during production testing, and provides that simulation time is reduced during design verification because the functional logic is not clocked.

7490307, Feb 10, 2009

Jun 29, 2006

11/478044

Giuseppe Fomaciari - Vimercate, IT
Fabio Mazza - Milan, IT
Cam Luong Lu - Milpitas CA, US
William Shen - San Jose CA, US

LSI Corporation - Milpitas CA

G06F 9/45
G06F 17/50

716 6, 716 4, 716 5

An apparatus comprising a database, an input module and a software tool. The database may be configured to generate one or more database files representing a design of an integrated circuit (IC). The input module may be configured to generate one or more test structures to test predetermined portions of the design of an IC. The software tool may be configured to automatically generate test scripts to verify timing constraints of the one or more test structures.

20050125755, Jun 9, 2005

Dec 3, 2003

10/728036

Cam Lu - Milpitas CA, US
Robert Benware - Ft. Collins CO, US
Thai Nguyen - San Jose CA, US

G06F017/50
G06F011/00

716006000, 703016000, 714042000

A method of generating a truncated scan test pattern for an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design; (b) estimating a number of transition delay fault test patterns and a corresponding number of top-off stuck-at fault patterns to achieve maximum stuck-at fault and transition delay fault coverage; (c) truncating the estimated number of transition delay fault patterns to generate a truncated set of transition delay fault patterns so that the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns achieve maximum stuck-at fault and transition delay fault coverage within a selected scan memory limit; and (d) generating as output the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns.

20130111285, May 2, 2013

Oct 27, 2011

13/283070

Sreejit Chakravarty - Mountain View CA, US
Cam Luong Lu - Milpitas CA, US

LSI Corporation - Milpitas CA

G01R 31/3177
G06F 11/25

714726, 714E11155

An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, with the scan chain being configured to operate as a serial shift register in a scan shift mode of operation and to capture functional data from at least a portion of the additional circuitry in a functional mode of operation. At least a given one of the scan cells of the scan chain comprises multiplexing circuitry configured to select one of multiple data lines of the scan cell for application to a functional output of the scan cell. For example, the multiplexing circuitry may comprise an output multiplexer configured to select between data outputs of master and slave flip-flops for connection to the functional output of the scan cell responsive to a test mode select.