Thomas E Obremski

6388930, May 14, 2002

Sep 5, 2001

09/946409

Thomas E. Obremski - South Burlington VT

International Business Machines Corporation - Armonk NY

G11C 2900

365201, 365236, 714718

A method for generating a selected subset of memory addresses associated with a semiconductor memory array is disclosed. In an exemplary embodiment of the invention, the method includes configuring an address counter to generate addresses corresponding to locations within the memory array. A mask register is programmed with a series of masking bits, the value of the masking bits determining whether corresponding address bits in the address counter are masked or not masked. Any of the address bits in the address counter corresponding to a masked bit are masked from a counting operation performed by the address counter, thereby causing the address counter to generate the selected subset of memory addresses.

6452848, Sep 17, 2002

Sep 12, 2001

09/950864

Thomas E. Obremski - South Burlington VT
Jeffrey H. Dreibelbis - Williston VT
Peter O. Jakobsen - Milton VT

International Business Machines Corporation - Armonk NY

G11C 2900

365201, 365240, 714718

A programmable data generator for generating input test data to be applied to a semiconductor memory array is disclosed. In an exemplary embodiment of the invention, the data generator includes a programmable address scramble register which has a plurality of storage locations associated therewith. The plurality of storage locations corresponds to array address bits associated with an address generator. A first exclusive OR (XOR) logic structure is coupled to the address generator and the address scramble register, wherein the first XOR logic structure generates an address-dependent, data scramble output signal that ultimately determines a data pattern to be applied to the memory array.

7073100, Jul 4, 2006

Nov 11, 2002

10/065694

Laura S. Chadwick - Essex Junction VT, US
William R. Corbin - Underhill VT, US
Jeffrey H. Dreibelbis - Williston VT, US
Erik A. Nelson - Waterbury VT, US
Thomas E. Obremski - South Burlington VT, US
Toshiharu Saitoh - South Burlington VT, US
Donald L. Wheater - Hinesburg VT, US

International Business Machines Corporation - Armonk NY

G11C 29/00

714718

A method and system for testing an embedded DRAM that includes DRAM blocks. The method including: generating a test data pattern in a processor based BIST system, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; where for each DRAM block, the write of the test data pattern into the DRAM block is performed before the pause, and the read of the resulting data pattern from each DRAM block is performed after the pause; where at least a portion of the pause of two or more of the DRAM blocks overlap in time; and for each DRAM block comparing the test data pattern to the resulting data pattern.

7237165, Jun 26, 2007

Nov 22, 2004

10/994496

Laura S. Chadwick - Essex Junction VT, US
William R. Corbin - Underhill VT, US
Jeffrey H. Dreibelbis - Williston VT, US
Erik A. Nelson - Waterbury VT, US
Thomas E. Obremski - South Burlington VT, US
Toshiharu Saitoh - South Burlington VT, US
Donald L. Wheater - Hinesburg VT, US

International Business Machines Corporation - Armonk NY

G01R 31/28
G11C 29/00

714733, 714718

A system for testing a DRAM includes DRAM blocks, the system further includes a processor based built-in self test system for generating a test data pattern, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block. For each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time, and at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.

57242950, Mar 3, 1998

Jun 7, 1995

8/473594

Mark Adam Beiley - Burlington VT
Charles Edward Drake - Underhill VT
Thomas Edward Obremski - South Burlington VT

International Business Machines Corporation - Armonk NY

G11C 700

365222

A small number of redundant circuits are freely allocable to any of a plurality of partitions or systems within an integrated circuit, such as a large dynamic random access memory (DRAM) consistent with the provision of parallel simultaneous refresh of corresponding addresses in all partitions or systems thereof. A valid address of a redundant circuit substituted for a partial address of a circuit in any partition or system is detected to disable refresh of that address in all partitions. The partition in which the substitution has been made is sensed and the disablement of refresh of all other partitions is overridden so that all partitions or systems in which a substitution has not been made may be refreshed concurrently with the substituted redundant circuit.