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Terry S Hulseweh

from Gilbert, AZ
Age ~78
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Also known as:
Terry Sydney Hulseweh
Related to:
Glen M Lyon, 52Eleanor I FrebergOlive M Beaird, 97Jeffrey B Hulseweh, 55Lisa L Pickel, 44Carla R Hulseweh, 77Sydney T HulsewehCr Hulseweh BeairdFrancis H HulsewehCarla Hulseweh
Connected to:
Ben I Hulsey, 65Bobbie Hulsey, 57Bobby W Hulsey, 47Brittany N Hulsey, 39Carter HulseyCheryl S Hulsey, 78Christen A Hulsey, 33Corey Hulsey, 35Dana L Hulsey, 54David S Hulsey, 45

Terry Hulseweh Phones & Addresses

  • Gilbert, AZ
  • 2349 Concho Ave, Mesa, AZ 85202
  • Phoenix, AZ
  • 8501 E Earll Dr, Scottsdale, AZ 85251 (480) 990-9963
  • Maricopa, AZ

Resumes

Resumes

Terry Hulseweh Photo 1

Terry Hulseweh

Publications

Us Patents

Method Of Forming Self-Aligned Implanted Channel-Stop And Buried Layer Utilizing Non-Single Crystal Alignment Key

US Patent:
45732574, Mar 4, 1986
Filed:
Sep 14, 1984
Appl. No.:
6/650931
Inventors:
Terry S. Hulseweh - Mesa AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2120
H01L 2174
H01L 2176
US Classification:
29576E
Abstract:
A process is described for fabricating self-aligned buried doped regions in semiconductor devices and integrated circuits which avoids any need for delineation of the buried doped regions in the active portions of the device. Avoiding delineation improves the quality of the epitaxial layer used to cover the buried doped regions thereby improving overall performance and yield. Multiple mask layers are used in connection with a single mask pattern to achieve self-alignment. One mask layer consists of a material with a modifiable etch rate, e. g. polysilicon. A portion of the single crystal substrate is rendered non-single crystal and used as an alignment key which is propagated through the epitaxial layer grown over the undelineated buried doped regions. The dimensions and separations of the self-aligned buried doped regions can be precisely controlled.

Method For Protecting A Semiconductor Device From Radiation Indirect Failures

US Patent:
44235488, Jan 3, 1984
Filed:
Jul 6, 1981
Appl. No.:
6/280190
Inventors:
Terry S. Hulseweh - Mesa AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2156
US Classification:
29591
Abstract:
A structure is provided which affords radiation protection to semiconductor devices and which specifically prevents soft failures in semiconductor memories caused by alpha particle radiation. The protection is provided by a metallic radiation shield formed on but insulated from the semiconductor memory array. The radiation shield is formed on the semiconductor devices while they are still in wafer form but after the normal device fabrication has been completed.

Process For Self-Aligned Buried Layer, Field Guard, And Isolation

US Patent:
45832820, Apr 22, 1986
Filed:
Sep 14, 1984
Appl. No.:
6/650969
Inventors:
Terry S. Hulseweh - Mesa AZ
Carroll Casteel - Mesa AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2180
H01L 2176
US Classification:
29576W
Abstract:
A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a polycrystalline semiconductor region, above a doped channel-stop region which acts as a field guard. A single mask layer determines the location and spacing of the buried portions of the isolation walls, the channel-stops, and the buried layers.

Pillar Via Process

US Patent:
46140212, Sep 30, 1986
Filed:
Mar 29, 1985
Appl. No.:
6/717343
Inventors:
Terry S. Hulseweh - Mesa AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 21312
US Classification:
29590
Abstract:
An improved means and method is described for providing a conductive pillar in a via between multiple layers of conductors on planar electronic structures such as integrated circuits. A lower first conductor layer is formed on the device substrate and covered with an electrically conducting etch-stop layer and a second conductor layer. The second conductor layer is masked to define the conductive via and etched selectively and anisotropically until the etch-stop layer is reached. The exposed portions of the etch-stop layer are then removed. The remaining portions of the etch-stop layer and second conductor layer together form the conductive pillar. The lower first metal layer is patterned and then covered with a planarizing layer, such as a polyimide, having a thickness at least equal to the height of the pillar. The planarizing layer is uniformly etched to expose the top of the pillar and then an upper metal layer deposited over the remaining polyimide and in contact with the top of the pillar. The remaining polyimide acts as the interlayer dielectric.

Epi Defect Reduction Using Rapid Thermal Annealing

US Patent:
47849649, Nov 15, 1988
Filed:
Oct 19, 1987
Appl. No.:
7/109684
Inventors:
Terry Hulseweh - Mesa AZ
Mel Miller - Mesa AZ
Assignee:
Motorola Inc. - Schaumburg IL
International Classification:
H01L 21265
H01L 21477
H01L 21324
US Classification:
437 26
Abstract:
Formation of defects in epi-layers above buried layers, particularly above arsenic buried layers, is substantially reduced by providing a brief high temperature Rapid Thermal Annealing (RTA) step after buried layer implantation, annealing-activation, and junction drive-in and before epi-layer growth. Among other things, the RTA step reduces the formation of arsenic precipitates which is frequently a consequence of slow cools commonly associated with conventional furnace activation-annealing, junction drive-in, and delineation oxidation prior to epi-layer growth.

Process For Self-Aligned Buried Layer, Channel-Stop, And Isolation

US Patent:
45744696, Mar 11, 1986
Filed:
Sep 14, 1984
Appl. No.:
6/650964
Inventors:
Sal Mastroianni - Tempe AZ
Carroll Casteel - Mesa AZ
Terry S. Hulseweh - Mesa AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2176
H01L 21223
H01L 2131
H01L 2174
US Classification:
29576W
Abstract:
A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a non-single crystal semiconductor region, above a doped channel-stop region. A single mask layer determines the location and spacing of the non-single crystal portion of the isolation walls, the channel-stops, and the buried layers.
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Terry S Hulseweh from Gilbert, AZ, age ~78 Get Report