Stanley Craig Beddingfield

6372622, Apr 16, 2002

Oct 26, 1999

09/426982

Qing Tan - Austin TX
Stanley Craig Beddingfield - Austin TX
Douglas G. Mitchell - Tempe AZ

Motorola, Inc. - Schaumburg IL

H01L 2144

438612, 438613, 438614, 22818022

Embodiments of the present invention relate generally to solder bump formation and semiconductor device assemblies. One embodiment related to a method for forming a bump structure includes providing a semiconductor device ( ) having a bond pad ( ), and forming a first masking layer ( ) overlying the bond pad ( ). The first masking layer ( ) is patterned to form a first opening ( ) overlying at least a portion of the bond pad ( ). A second masking layer ( ) is formed overlying the first masking layer ( ), and the second masking layer ( ) is patterned to form a second opening ( ) overlying at least a portion of the first opening ( ). The method further includes forming a stud ( ) at least within the first opening ( ) and a solder bump ( ) at least within the second opening ( ).

7741567, Jun 22, 2010

May 19, 2008

12/123115

Stanley Craig Beddingfield - McKinney TX, US
Jean-Francois Drouard - Lerouret, FR

Texas Instruments Incorporated - Dallas TX

H05K 9/00

174386, 361818, 257659, 257686

A packaged integrated circuit (IC) () includes a first substrate () including a first plurality of layers and first circuit coupling features () at an upper surface of the first substrate (). The first plurality of layers include a first electromagnetic interference shielding layer (). The packaged IC also includes a second substrate () having an upper surface attached to a lower surface of the first substrate () by an electrically conductive adhesive material (). The second substrate () includes a second plurality of layers and a second circuit coupling feature () at a lower surface of the second substrate (). The first plurality of layers includes a second EMI shielding layer (). The packaged IC further includes a functional die () disposed between the first () and the second () substrates and functionally coupled to the first () and/or the second () circuit coupling features. In the packaged IC, the adhesive material () electrically couples the first () and the second () shielding layers.

8049119, Nov 1, 2011

May 7, 2010

12/775875

Stanley C Beddingfield - McKinney TX, US
Jean-Francois Drouard - LeRouret, FR

Texas Instruments Incorporated - Dallas TX

H05K 9/00

174386, 361818, 257659, 257686

A packaged integrated circuit (IC) () includes a first substrate () comprising a first plurality of layers and a first circuit coupling features () at an upper surface of the first substrate (), the first plurality of layers including a first electromagnetic interference shielding layer (). The packaged IC also includes a second substrate () having an upper surface attached to a lower surface of the first substrate () by an electrically conductive adhesive material (). The second substrate () includes a second plurality of layers and a second circuit coupling feature () at a lower surface of the second substrate (). The first plurality of layer includes a second EMI shielding layer (). The packaged IC further includes a functional die () disposed between the first () and the second () substrates and functionally coupled to the first () and/or the second () circuit coupling features. In the packaged IC, the adhesive material () electrically couples the first () and the second () shielding layers.

8304867, Nov 6, 2012

Nov 1, 2010

12/917144

Robert Fabian McCarthy - Dallas TX, US
Stanley Craig Beddingfield - McKinney TX, US

Texas Instruments Incorporated - Dallas TX

H01L 23/495

257669, 257673, 257727, 257780, 257786, 257E23169

An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of I/O nodes. A first dielectric layer including first dielectric vias is over the plurality of die pads. A redirect layer (RDL) including a plurality of RDL capture pads is coupled to the plurality of die pads over the first dielectric vias. A second dielectric layer including second dielectric vias is over the plurality of RDL capture pads. At least one of the second dielectric vias is a crack arrest via that has a via shape that includes an apex that faces away from a neutral stress point of the IC die and is oriented along a line from the neutral stress point to the crack arrest via to face in a range of 30 degrees from the line. Under bump metallization (UBM) pads are coupled to the plurality of RDL capture pads over the second dielectric vias, and metal bonding connectors are on the UBM pads.

20070023910, Feb 1, 2007

Jul 29, 2005

11/192876

Stanley Beddingfield - McKinney TX, US

H01L 23/48

257738000

A method of improving the performance of a ball grid array package under temperature cycling and drop tests is disclosed. The method comprises forming a ball grid array with two types of solder balls. The first type of ball has a composition that improves performance under temperature cycling and the second set of solder balls has a composition that improves performance under drop testing. Preferably, the first set of balls is under the die near its perimeter and the second set of balls is located near the package perimeter, particularly at corners. A related concept pertains to a semiconductor device comprising a printed circuit board and a ball grid array package attached to the printed circuit board by an array of solder balls. The solder ball array comprises first and second sets of solder balls, the two sets having distinctly different compositions.

20070029661, Feb 8, 2007

Aug 4, 2005

11/198543

Stanley Craig Beddingfield - McKinney TX, US
Kevin Peter Lyne - Plano TX, US
Peter Harper - Lucas TX, US

H01L 23/52
H01L 21/44

257691000, 257698000, 257700000, 438614000

According to one embodiment of the invention, a power system for a die comprises a plurality of supply voltage lines, a plurality of ground lines, a plurality of metallized rails, and a via. Each of the plurality of supply voltage lines are in communication with at least one supply voltage pad. Each of the plurality of ground lines are in communication with at least one ground pad. The plurality of ground lines are interlaced with the plurality of supply voltage lines. The plurality of metallized rails are disposed across the plurality of supply voltage lines and the plurality of ground lines. The via communicatively couples at least one of the plurality of metallized rails to at least one of the supply voltage lines or at least one of the ground lines.

20090140401, Jun 4, 2009

Nov 30, 2007

11/948924

Stanley Craig Beddingfield - McKinney TX, US
Orlando Florendo Torres - Richardson TX, US
Robert Fabian McCarthy - Dallas TX, US

H01L 23/495
H01L 21/58

257666, 438123, 257E21499, 257E23039

An integrated circuit package includes a die, a bump, an underbump metallization layer formed between the bump and the die, a portion of the underbump metallization layer under the bump having a first radius, and a redistribution layer formed between the underbump metallization layer and the die. The redistribution layer has a pad positioned under the underbump metallization layer. The pad has a second radius, and makes contact with the underbump metallization layer. The second radius is less than or equal to the first radius. The integrated circuit package also includes a first dielectric layer disposed between the die and the redistributing layer.

20090278263, Nov 12, 2009

May 9, 2008

12/118078

Robert Fabian McCarthy - Dallas TX, US
Stanley Craig Beddingfield - McKinney TX, US

H01L 23/52
G06F 9/455

257778, 716 11, 257E23141

An integrated circuit device includes a functional circuit die with a patterned rewiring layer defining a first rewiring pad and one or more second rewiring pads on opposite sides of a neutral point of the die. The device also includes at least one dielectric layer having bump opening features over the rewiring pads. The device further includes electrically conductive bump pad features formed on the dielectric layer over the bump opening features. The bump pad features make contact with the rewiring pads via the bump opening features. In the device, a center of the bump opening features are laterally offset from a center of the bump pad feature towards a neutral point of the die.