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Srivatsan Chellappa

from San Diego, CA
Age ~43
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Related to:
John V ChellappaPaul ChellappaJonathan Daniel Tapia, 34Justin M Tapia, 28Balaji N Chellappa, 38
Connected to:
Kasi Chellappa, 65Malathi K Chellappan, 52Rajan Chellappa, 51Saravanan Chellappan, 44Thiagarajan Chellappan, 53Edward F Chellel, 101Brenda B Chellew, 64Doug A Chellevold, 50Nicole T Chellew, 53Bobby Chelley, 43

Srivatsan Chellappa Phones & Addresses

  • San Diego, CA
  • Tempe, AZ

Work

Company: Arizona state university Aug 2008 Position: Student research aide

Education

Degree: MS School / High School: Arizona State University 2007 to 2009 Specialities: Electrical Engineering

Skills

Development • Semiconductors • Design • Research • Vlsi Design • Engineering • Software

Industries

Semiconductors

Resumes

Resumes

Srivatsan Chellappa Photo 1

Senior Engineer

Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
Arizona State University since Aug 2008
Student Research Aide
Arizona State University Aug 2007 - May 2009
Math and Engineering Tutor
Arizona State University Aug 2007 - May 2009
Graduate Student
Education:
Arizona State University 2007 - 2009
MS, Electrical Engineering Anna University 2003 - 2007
Bachelor, Engineering; Electrical and Electronics Engineering
Skills:
Development
Semiconductors
Design
Research
Vlsi Design
Engineering
Software

Publications

Us Patents

Sram Circuits For Circuit Identification Using A Digital Fingerprint

US Patent:
20120230087, Sep 13, 2012
Filed:
Mar 8, 2012
Appl. No.:
13/415599
Inventors:
Srivatsan Chellappa - Tempe AZ, US
Lawrence T. Clark - Phoenix AZ, US
Assignee:
ARIZONA TECHNOLOGY ENTERPRISES, LLC - Scottsdale AZ
International Classification:
G11C 11/00
US Classification:
365154
Abstract:
Circuitry that includes static random access memory (SRAM) access circuitry and a group of SRAM memory cells is disclosed. A digital fingerprint of the group of SRAM memory cells is determined by using the SRAM access circuitry to force at least a portion of the group of SRAM memory cells into a metastable state and then releasing the portion of the SRAM memory cells. Each SRAM memory cell that was released then selects one of two stable states and the SRAM access circuitry provides a selection profile based on the selections. The digital fingerprint is based on the selection profile.

True Random Number Generator Based On Period Jitter

US Patent:
20210405973, Dec 30, 2021
Filed:
Jun 26, 2020
Appl. No.:
16/913631
Inventors:
- San Diego CA, US
De LU - San Diego CA, US
Venkat NARAYANAN - San Diego CA, US
Srivatsan CHELLAPPA - San Diego CA, US
International Classification:
G06F 7/58
Abstract:
A true random number generator (TRNG) for generating a sequence of random numbers of bits is disclosed. The TRNG includes a TRNG cell configured to generate a sequence of bits logically alternating with a mean frequency and with substantially random period jitter; a period monitor configured to generate a first sequence of random bits based on a set of periods of the sequence of logically alternating bits; and a sampling circuit configured to sample the first sequence of random bits in response to a sampling clock to generate a second sequence of random bits.

Configurable Mac For Neural Network Applications

US Patent:
20210110267, Apr 15, 2021
Filed:
Oct 11, 2019
Appl. No.:
16/599306
Inventors:
- San Diego CA, US
Srivatsan CHELLAPPA - San Diego CA, US
Seung Hyuk KANG - San Diego CA, US
International Classification:
G06N 3/08
G06N 3/063
G06F 7/544
Abstract:
Certain aspects of the present disclosure are directed to methods and apparatus for configuring a multiply-accumulate (MAC) block in an artificial neural network. A method generally includes receiving, at a neural processing unit comprising one or more logic elements, at least one input associated with a use-case of the neural processing unit; obtaining a set of weights associated with the at least one input; selecting a precision for the set of weights; modifying the set of weights based on the selected precision; and generating an output based, at least in part, on the at least one input, the modified set of weights, and an activation function.

Muller C-Element As Majority Gate For Self-Correcting Triple Modular Redundant Logic With Low-Overhead Modes

US Patent:
20170117895, Apr 27, 2017
Filed:
Oct 24, 2016
Appl. No.:
15/332593
Inventors:
Lawrence T. Clark - Phoenix AZ, US
Srivatsan Chellappa - Tempe AZ, US
Vinay Vashishtha - Tempe AZ, US
Aditya Gujja - Tempe AZ, US
Assignee:
Arizona Board of Regents on behalf of Arizona State University - Scottsdale AZ
International Classification:
H03K 19/003
H03K 19/096
H03K 3/037
Abstract:
Embodiments of an sequential state element (SSE) capable of providing triple modular redundant (TMR) correction is disclosed. The SSE has a setup stage and a feedback stage. The setup stage is configured to generate an output bit signal having an output bit state while a clock signal is in the first clock state. The setup stage also generates a feedback input bit signal as feedback of the output bit state. However, the feedback stage is capable of providing TMR correction without this feedback signal. Instead, the feedback stage utilizes the second feedback input bit signal and a third feedback input bit signal from two other SSEs. Since TMR correction can be provided with just the second feedback input bit signal and the third feedback input bit signal, the power and area consumed by the SSE is reduced.

Hierarchical In-Memory Sort Engine

US Patent:
20160171045, Jun 16, 2016
Filed:
Mar 7, 2016
Appl. No.:
15/063315
Inventors:
- Armonk NY, US
Srivatsan Chellappa - Tempe AZ, US
Toshiaki Kirihata - Poughkeepsie NY, US
Karthik V. Swaminathan - State College PA, US
International Classification:
G06F 17/30
Abstract:
A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.

Techniques For Generating Physical Layouts Of In Silico Multi Mode Integrated Circuits

US Patent:
20150363517, Dec 17, 2015
Filed:
Jun 15, 2015
Appl. No.:
14/739347
Inventors:
Lawrence T. Clark - Phoenix AZ, US
Dan Wheeler Patterson - Scottsdale AZ, US
Srivatsan Chellappa - Tempe AZ, US
Assignee:
Arizona Board of Regents on behalf of Arizona State University - Scottsdale AZ
International Classification:
G06F 17/50
Abstract:
This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing.

Hierarchical In-Memory Sort Engine

US Patent:
20150347592, Dec 3, 2015
Filed:
Jun 3, 2014
Appl. No.:
14/294710
Inventors:
- Armonk NY, US
Srivatsan Chellappa - Tempe AZ, US
Toshiaki Kirihata - Poughkeepsie NY, US
Karthik V. Swaminathan - State College PA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/30
G06F 12/08
Abstract:
A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.

Electronic Circuit For Fitting A Virtual Address Range To A Physical Memory Containing Faulty Address

US Patent:
20150089329, Mar 26, 2015
Filed:
Sep 26, 2013
Appl. No.:
14/037487
Inventors:
- Armonk NY, US
Srivatsan Chellappa - Tempe AZ, US
Dean L. Lewis - Williston VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/10
US Classification:
714773
Abstract:
A memory having variable size blocks of failed memory addresses is connected to a TCAM storing data values of ranges of addresses in the memory. The ranges of addresses correspond to virtual addresses that, in combination with an offset, point away from failed memory addresses. A reduction circuit connected to the TCAM produces an output for each programmed range of addresses based on a virtual address. A priority encoder, connected to the reduction circuit, selects a first range from the reduction circuit and passes the first range to a random-access memory (RAM). Responsive to the virtual address bring an address in one of the ranges of addresses, the priority encoder passes the first range containing the virtual address to the RAM, which passes a corresponding offset value to the Adder based on the first range. The Adder calculates a physical memory address directing the virtual address to a functional memory location.
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Srivatsan Chellappa from San Diego, CA, age ~43 Get Report