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Rohan N Akolkar

from Moreland Hills, OH
Age ~44
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Also known as:
Rohan Narayan Akolkar, Rohan Narayan Te Akolkar
Phone and address:
50 Fairway Trl, Orange Village, OH 44022
Connected to:
Ojas R Akolkar, 50Eric M Akombe, 37Princella Akomeah, 49Abiodun Akomolafe, 40Olumide K Akomolede, 33Arie T Akompi, 30Barbara C Akon, 67Duane S Akon, 52Monir U Akon, 51Joanne F Akong, 48

Rohan Akolkar Phones & Addresses

  • 50 Fairway Trl, Chagrin Falls, OH 44022
  • Moreland Hills, OH
  • 2500 Derbyshire Rd, Cleveland, OH 44106 (216) 397-6523
  • Beachwood, OH
  • 2543 Overlook Dr, Hillsboro, OR 97124
  • 5667 NE Orenco Gardens Dr, Hillsboro, OR 97124
  • Seattle, WA

Resumes

Resumes

Rohan Akolkar Photo 1

Rohan Akolkar

Publications

Us Patents

Dual Metal Interconnects For Improved Gap-Fill, Reliability, And Reduced Capacitance

US Patent:
7867891, Jan 11, 2011
Filed:
Dec 10, 2008
Appl. No.:
12/316304
Inventors:
Kevin O'brien - Portland OR, US
Rohan Akolkar - Hillsboro OR, US
Tejaswi Indukuri - Hillsboro OR, US
Arnel M. Fajardo - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/4763
H01L 21/44
US Classification:
438629, 438677, 438678
Abstract:
Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed.

Electroless Cu Plating For Enhanced Self-Forming Barrier Layers

US Patent:
8138084, Mar 20, 2012
Filed:
Dec 23, 2009
Appl. No.:
12/646618
Inventors:
Rohan N. Akolkar - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/44
H01L 21/4763
US Classification:
438653, 438643, 438660, 438687, 438678, 438652, 257E21585, 257751
Abstract:
Methods and an apparatus are described for an integrated circuit within which an electroless Cu plated layer having an oxygen content is formed on the top of a seed layer comprising Cu and Mn. The integrated circuit is then exposed to a sufficient high temperature to cause the self-formation of a MnSiOx barrier layer.

Barrier Layers

US Patent:
8508018, Aug 13, 2013
Filed:
Sep 24, 2010
Appl. No.:
12/890462
Inventors:
Rohan N. Akolkar - Hillsboro OR, US
Sridhar Balakrishnan - Rio Rancho NM, US
James S. Clarke - Hillsboro OR, US
Christopher J. Jezewski - Hillsboro OR, US
Philip Yashar - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/00
US Classification:
257508, 257513, 257520
Abstract:
Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.

Electroplating Chemistries And Methods Of Forming Interconnections

US Patent:
20070267297, Nov 22, 2007
Filed:
May 17, 2006
Appl. No.:
11/383925
Inventors:
Rohan Akolkar - Hillsboro OR, US
Valery Dubin - Portland OR, US
International Classification:
C25D 5/02
US Classification:
205118000
Abstract:
A method comprising forming an interconnection opening through a dielectric material to a contact point; and electroplating a interconnection comprising copper in the contact opening using an electroplating bath comprising an alkoxylated sulfopropylated alkylamine. A method comprising forming an interconnection opening through a dielectric material to a contact point; lining the interconnection opening with a barrier layer and a seed layer; and electroplating an interconnection comprising copper in the contact opening using an electroplating bath comprising an alkoxylated sulfopropylated alkylamine.

Sacrificial Tapered Trench Opening For Damascene Interconnects

US Patent:
20080026555, Jan 31, 2008
Filed:
Jul 26, 2006
Appl. No.:
11/494389
Inventors:
Valery M. Dubin - Portland OR, US
Rohan N. Akolkar - Hillsboro OR, US
Scott B. Clendenning - Portland OR, US
International Classification:
H01L 21/44
US Classification:
438597
Abstract:
A method for forming a trench with a flared opening in a dielectric layer comprises providing a semiconductor substrate having a dielectric layer deposited thereon, depositing and patterning a photoresist layer atop the dielectric layer to form at least two photoresist structures, applying a plasma etch to define a flared trench profile in the photoresist structures, and applying a dry etch chemistry to etch a trench in the dielectric layer using the photoresist structures as a mask, wherein the flared trench profile is transferred from the photoresist structures to the dielectric layer. The dry etch chemistry may comprise an anisotropic plasma etch.

Method Of Fabricating Metal Interconnects Using A Sacrificial Layer To Protect Seed Layer Prior To Gap Fill

US Patent:
20080113508, May 15, 2008
Filed:
Nov 13, 2006
Appl. No.:
11/598889
Inventors:
Rohan N. Akolkar - Hillsboro OR, US
Florian Gstrein - Portland OR, US
Valery M. Dubin - Portland OR, US
Daniel J. Zierath - Portland OR, US
International Classification:
H01L 21/44
US Classification:
438687
Abstract:
Disclosed are embodiments of a method of forming metal interconnects using a sacrificial layer to protect a seed layer prior to metal gap fill. The sacrificial layer can prevent oxidation of the seed layer and perhaps oxygen migration to an underlying barrier layer. Other embodiments are described and claimed.

Copper Metallization Utilizing Reflow On Noble Metal Liners

US Patent:
20090169760, Jul 2, 2009
Filed:
Dec 31, 2007
Appl. No.:
11/968136
Inventors:
Rohan Akolkar - Hillsboro OR, US
Florian Gstrein - Portland OR, US
Boyan Boyanov - Portland OR, US
Sridhar Balakrishnan - Portland OR, US
International Classification:
C23C 4/06
B05D 5/12
US Classification:
427455, 427123, 427125
Abstract:
Methods for making copper (Cu) interconnects in semiconductor devices for interconnect dimensions less than 50 nm are described. The processes form Cu interconnects using a sequence of barrier layer, liner layer, and Cu deposition layer depositions, followed by a thermally assisted Cu reflow of the Cu deposition layer, and then a chemical mechanical polish (CMP) to removed excess portions of the reflowed Cu. The liner layer comprises noble metals such as Ru, Ir, Os, Rh, Re, Pd, Pt, and Au. Such processes avoids the formation of voids in copper interconnects with dimensions less than 50 nm.

Dopant Enhanced Interconnect

US Patent:
20100200991, Aug 12, 2010
Filed:
Feb 12, 2010
Appl. No.:
12/705143
Inventors:
Rohan Akolkar - Hillsboro OR, US
Sridhar Balakrishnan - Portland OR, US
Adrien R. Lavoie - Beaverton OR, US
Tejaswi K. Indukuri - Hillsboro OR, US
James S. Clarke - Portland OR, US
International Classification:
H01L 23/532
H01L 21/768
US Classification:
257751, 438643, 257E23161, 257E21584
Abstract:
Techniques are disclosed that enable an interconnect structure that is resistance to electromigration. A liner is deployed underneath a seed layer of the structure. The liner can be a thin continuous and conformal layer, and may also limit oxidation of an underlying barrier (or other underlying surface). A dopant that is compatible (non-alloying, non-reactive) with the liner is provided to alloy the seed layer, and allows for dopant segregation at the interface at the top of the seed layer. Thus, electromigration performance is improved.
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Rohan N Akolkar from Moreland Hills, OH, age ~44 Get Report