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Laiq K Chughtai

from Danville, CA
Age ~50
Get Report
Also known as:
Laiq K Chughtal
Phone and address:
110 Parkhaven Dr, Danville, CA 94506
Related to:
Laiq Chughtai Maidah, 46Mohammad ChughtaiKhalid Chughtai, 89Maidah L Chughtai, 46Saba A Chughtai, 61Y L ChughtaiMustafa Z Khalid, 32Munir Chughtai, 96Mohammad A KhalidMohammad A Khalid, 63
Connected to:
Bushra I Chughtai, 62Mohsin ChughtaiNabeel Chughtai, 41Shahid I Chughtai, 47Shelia A Chughtai, 54Zenaida A Chughtai, 81Lisa A Chugranis, 57David L Chuhay, 43James E Chuhran, 77John J Chuhran, 80

Laiq Chughtai Phones & Addresses

  • 110 Parkhaven Dr, Danville, CA 94506
  • Fremont, CA
  • 1700 1St St, San Jose, CA 95112 (408) 392-9081
  • 402 Galleria Dr APT 12, San Jose, CA 95134
  • Milpitas, CA
  • Charlotte, NC
  • Palatine, IL
  • Madison, WI
  • Westminster, CA
  • Campbell, CA

Resumes

Resumes

Laiq Chughtai Photo 1

Management Consultant With Deep Experience In Hi-Tech Management

Position:
Manager at Alvarez & Marsal
Location:
San Francisco Bay Area
Industry:
Management Consulting
Work:
Alvarez & Marsal - San Francisco Bay Area since Nov 2012
Manager
Alvarez & Marsal - San Francisco Bay Area Sep 2011 - Nov 2012
Consultant
Altera Corporation Apr 1999 - Aug 2011
Manager, Product Engineering
Motorola Mobility - Arlington Heights, IL May 1998 - Aug 1998
Engineering Intern
ScheduleSoft Corporation - Madison, WI Jan 1997 - Dec 1997
Software Engineering Intern
Education:
University of California, Berkeley - Walter A. Haas School of Business 2007 - 2010
MBA, General Management University of Wisconsin-Madison 1996 - 1998
BS, Electrical & Computer Engineering Illinois Institute of Technology 1994 - 1996
BS, Electrical Engineering
Skills:
Cross-functional Team Leadership
Product Management
Program Management
Product Development
Semiconductors
Business Strategy
Project Management
Engineering Management
Interests:
Skiing, Volleyball, Volunteering
Honor & Awards:
- US Patent Number 7212032: Method and apparatus for monitoring yield of integrated circuits - US Patent Number 7685485: Functional failure analysis techniques for programmable integrated circuits - Multiple recognitions at Altera for technical skill, leadership, initiative and follow-through.
Laiq Chughtai Photo 2

Director Performance Improvement And Corporate Transformation At Tivo

Location:
110 Parkhaven Dr, Danville, CA 94506
Industry:
Information Technology And Services
Work:
Alvarez & Marsal - San Francisco Bay Area since Nov 2012
Manager
Alvarez & Marsal - San Francisco Bay Area Sep 2011 - Nov 2012
Consultant
Altera Corporation Apr 1999 - Aug 2011
Manager, Product Engineering
Motorola Mobility - Arlington Heights, IL May 1998 - Aug 1998
Engineering Intern
ScheduleSoft Corporation - Madison, WI Jan 1997 - Dec 1997
Software Engineering Intern
Education:
University of California, Berkeley - Walter A. Haas School of Business 2007 - 2010
MBA, General Management University of Wisconsin-Madison 1996 - 1998
BS, Electrical & Computer Engineering Illinois Institute of Technology 1994 - 1996
BS, Electrical Engineering
Skills:
Product Development
Management
Product Management
Program Management
Cross Functional Team Leadership
Semiconductors
Strategy
Leadership
Telecommunications
Project Management
Business Strategy
Engineering Management
Software Development
Integration
Software Engineering
Mobile Devices
Ic
Asic
Soc
Interests:
Education
Languages:
English

Publications

Us Patents

Functional Failure Analysis Techniques For Programmable Integrated Circuits

US Patent:
7685485, Mar 23, 2010
Filed:
Oct 30, 2003
Appl. No.:
10/698739
Inventors:
Binh Vo - San Jose CA, US
Wan-Pin Hung - Saratoga CA, US
David Huang - Fremont CA, US
Peter Boyle - Mountain View CA, US
Qi Richard Chen - Sunnyvale CA, US
Kaiyu Ren - San Jose CA, US
Adam J. Wright - San Jose CA, US
John DiCosola - Pleasanton CA, US
Laiq Chughtai - Fremont CA, US
Seng Yew Lim - Penang, MY
Assignee:
Altera Corporation - San Jose CA
International Classification:
G01R 31/28
US Classification:
714725, 714 25
Abstract:
Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.

Method And Apparatus For Monitoring Yield Of Integrated Circuits

US Patent:
7212032, May 1, 2007
Filed:
Apr 25, 2006
Appl. No.:
11/411310
Inventors:
Jayabrata Ghosh Dastidar - San Jose CA, US
Laiq Chughtai - San Jose CA, US
William Y. Hata - Saratoga CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 19/173
US Classification:
326 38, 326 10
Abstract:
A method for analyzing a structured integrated circuit is provided. The method includes identifying a random logic region of the structured integrated circuit. The structured integrated circuit includes a predefined layout for transistors and basic interconnections to define a set of logic elements. A tile array of basic logic cells is integrated throughout the identified random logic region. The tile array of basic logic cells is defined from the set of logic elements of the structured integrated circuit. The tile array of basic cells enables communication of testing signals along the tile array of basic logic cells in a first and a second direction. The first and second directions are different from one another. The testing signals help to identify one or more errors in the tile array of basic logic cells. The array format assists in diagnosing and curing defects in the tile array of basic logic cells.
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Laiq K Chughtai from Danville, CA, age ~50 Get Report