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John Andrew Gunnels

from Somers, NY
Age ~59
Get Report
Also known as:
John A Gunnels
Phone and address:
10 Londonderry Ln, Somers Town, NY 10589
(914) 244-6233
Related to:
Ronda L GunnelsThomas J Lehnertz, 52William Lehnertz, 39William Gunnels, 30Theresa Gunnels
Connected to:
Ariel K Gunnels, 36Brad O Gunnels, 63Carl W Gunnels, 45Clyde GunnelsCory Gunnels, 42Cynthia A Gunnels, 67Frank N Gunnels, 58James J Gunnels, 94Kathy G Gunnels, 65Kellen G Gunnels, 37

John Gunnels Phones & Addresses

  • 10 Londonderry Ln, Somers, NY 10589 (914) 244-6233
  • Yorktown Heights, NY
  • 85 Foxwood Cir, Mount Kisco, NY 10549
  • Redmond, OR
  • 1006 Village Dr, Brewster, NY 10509
  • Austin, TX
  • Bend, OR
  • Yorktown Hts, NY
  • Westchester, NY

Resumes

Resumes

John Gunnels Photo 1

Principal Engineer At Aws

Location:
Yorktown Heights, NY
Industry:
Research
Work:
Amazon Web Services
Principal Engineer at Aws
Ibm
Distinguished Research Staff Member, Manager, Senior Manager, and Program Director at Ibm Research
Education:
Texas State University
Bachelors The University of Texas at Austin
Doctorates, Doctor of Philosophy, Computer Science
Skills:
High Performance Computing
Algorithms
Distributed Systems
Parallel Computing
Scalability
Computer Science
Parallel Programming
Software Engineering
Simulations
Software Development
Big Data
Optimization
Linux
Data Mining
Machine Learning
C
Python
Cloud Computing
C++
Unix
Analytics
Hadoop
Shell Scripting
Scientific Computing
High Performance Computing
Mpi
Computer Architecture
Management
Mathematical Programming
Fortran
Java
Mathematica
Research
Ibm Power
Multithreaded Application Development
Molecular Dynamics
Assembly Language
Latex
System Architecture
Matlab
Large Scale Optimization
Programming
Architecture
Scheme
Lisp
Interests:
Children
Environment
Education
Science and Technology
Disaster and Humanitarian Relief
Animal Welfare
Health
Certifications:
Introduction To Quantum Computing
Quantum Algorithms For Cybersecurity, Chemistry, and Optimization
Practical Realities of Quantum Computation and Quantum Communication
Requirements For Large-Scale Universal Quantum Computation
Applications of Quantum Computing
Patent Issuance
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John Gunnels

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John Ed Gunnels

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John Gunnels

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John Gunnels

Publications

Us Patents

Method And Structure For An Improved Data Reformatting Procedure

US Patent:
7555604, Jun 30, 2009
Filed:
Jan 9, 2006
Appl. No.:
11/328344
Inventors:
Siddhartha Chatterjee - Yorktown Heights NY, US
John A. Gunnels - Brewster NY, US
Fred Gehrung Gustavson - Briarcliff Manor NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/12
US Classification:
711118
Abstract:
A method (and structure) of managing memory in which a low-level mechanism is executed to signal, in a sequence of instructions generated at a higher level, that at least a portion of a contiguous area of memory is permitted to be overwritten.

Performance Evaluation Of Algorithmic Tasks And Dynamic Parameterization On Multi-Core Processing Systems

US Patent:
7793011, Sep 7, 2010
Filed:
May 29, 2008
Appl. No.:
12/129245
Inventors:
John A. Gunnels - Yorktown Heights NY, US
Shakti Kapoor - Austin TX, US
Ravi Kothari - New Delhi, IN
Yogish Sabharwal - New Delhi, IN
James C. Sexton - Danbury CT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 13/28
G06F 11/30
G06F 9/455
G06G 7/62
US Classification:
710 22, 710 23, 710 28, 702182, 702186, 703 13, 703 23
Abstract:
A method for evaluating performance of DMA-based algorithmic tasks on a target multi-core processing system includes the steps of: inputting a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; evaluating performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and providing results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system.

Method And Structure For Fast In-Place Transformation Of Standard Full And Packed Matrix Data Formats

US Patent:
7844630, Nov 30, 2010
Filed:
Feb 19, 2008
Appl. No.:
12/033581
Inventors:
Fred Gehrung Gustavson - Briarcliff Manor NY, US
John A. Gunnels - Yorktown Heights NY, US
James C. Sexton - Danbury CT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/00
US Classification:
707791, 707802, 707822, 707828
Abstract:
A computerized method provides for an in-place transformation of matrix A data including a New Data Structure (NDS) format and a transformation T having a compact representation. The NDS represents data of the matrix A in a format other than a row major format or a column major format, such that the data for the matrix A is stored as contiguous sub matrices of size MB by NB in an order predetermined to provide the data for a matrix processing. The transformation T is applied to the MB by NB blocks, using an in-place transformation processing, thereby replacing data of the block A with the contents of T(A).

System And Method For Detecting A Faulty Object In A System

US Patent:
7853820, Dec 14, 2010
Filed:
Oct 22, 2008
Appl. No.:
12/256355
Inventors:
John A. Gunnels - Brewster NY, US
Fred Gehrung Gustavson - Briarcliff Manor NY, US
Robert Daniel Engle - St. Louis MO, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/00
US Classification:
714 4, 709223, 709224
Abstract:
A method (and system) for detecting at least one faulty object in a system including a plurality of objects in communication with each other in an n-dimensional architecture, includes probing a first plane of objects in the n-dimensional architecture and probing at least one other plane of objects in the n-dimensional architecture which would result in identifying a faulty object in the system.

Performance Evaluation Of Algorithmic Tasks And Dynamic Parameterization On Multi-Core Processing Systems

US Patent:
8037215, Oct 11, 2011
Filed:
May 30, 2008
Appl. No.:
12/130167
Inventors:
John A. Gunnels - Yorktown Heights NY, US
Shakti Kapoor - Austin TX, US
Ravi Kothari - New Delhi, IN
Yogish Sabharwal - New Delhi, IN
James C. Sexton - Danbury CT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 13/28
G06F 17/50
US Classification:
710 22, 710 23, 710 24, 710 25, 710 26, 710 27, 710 28, 703 13
Abstract:
Apparatus for evaluating the performance of DMA-based algorithmic tasks on a target multi-core processing system includes a memory and at least one processor coupled to the memory. The processor is operative: to input a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; to evaluate performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and to provide results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system.

Method And Structure For Skewed Block-Cyclic Distribution Of Lower-Dimensional Data Arrays In Higher-Dimensional Processor Grids

US Patent:
8055878, Nov 8, 2011
Filed:
Feb 8, 2005
Appl. No.:
11/052216
Inventors:
Siddhartha Chatterjee - Yorktown Heights NY, US
John A. Gunnels - Brewster NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 15/00
US Classification:
712 10
Abstract:
A method and structure of distributing elements of an array of data in a computer memory to a specific processor of a multi-dimensional mesh of parallel processors includes designating a distribution of elements of at least a portion of the array to be executed by specific processors in the multi-dimensional mesh of parallel processors. The pattern of the designating includes a cyclical repetitive pattern of the parallel processor mesh, as modified to have a skew in at least one dimension so that both a row of data in the array and a column of data in the array map to respective contiguous groupings of the processors such that a dimension of the contiguous groupings is greater than one.

Reducing Bandwidth Requirements For Matrix Multiplication

US Patent:
8250130, Aug 21, 2012
Filed:
May 30, 2008
Appl. No.:
12/129789
Inventors:
Daniel A. Brokenshire - Round Rock TX, US
John A. Gunnels - Yorktown Heights NY, US
Michael D. Kistler - Pflugerville TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/16
US Classification:
708607
Abstract:
A block matrix multiplication mechanism is provided for reversing the visitation order of blocks at corner turns when performing a block matrix multiplication operation in a data processing system. The mechanism increases block size and divides each block into sub-blocks. By reversing the visitation order, the mechanism eliminates a sub-block load at the corner turns. The mechanism performs sub-block matrix multiplication for each sub-block in a given block, and then repeats operation for a next block until all blocks are computed. The mechanism may determine block size and sub-block size to optimize load balancing and memory bandwidth. Therefore, the mechanism reduces maximum throughput and increases performance. In addition, the mechanism also reduces the number of multi-buffered local store buffers.

Optimized Scalar Promotion With Load And Splat Simd Instructions

US Patent:
8255884, Aug 28, 2012
Filed:
Jun 6, 2008
Appl. No.:
12/134495
Inventors:
Alexandre E. Eichenberger - Chappaqua NY, US
Michael K. Gschwind - Chappaqua NY, US
John A. Gunnels - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/45
G06F 9/44
US Classification:
717136, 717106, 717141, 717144, 717146, 717149, 712 4
Abstract:
Mechanisms for optimizing scalar code executed on a single instruction multiple data (SIMD) engine are provided. Placement of vector operation-splat operations may be determined based on an identification of scalar and SIMD operations in an original code representation. The original code representation may be modified to insert the vector operation-splat operations based on the determined placement of vector operation-splat operations to generate a first modified code representation. Placement of separate splat operations may be determined based on identification of scalar and SIMD operations in the first modified code representation. The first modified code representation may be modified to insert or delete separate splat operations based on the determined placement of the separate splat operations to generate a second modified code representation. SIMD code may be output based on the second modified code representation for execution by the SIMD engine.

Isbn (Books And Publications)

Using Plapack: Parallel Linear Algebra Package

Author

John Gunnels

ISBN #

0262720264

Control profile
John Andrew Gunnels from Somers, NY, age ~59 Get Report