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Jason R Bergendahl

from Lenox, MA
Age ~51
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Also known as:
Jason Robert Bergendahl, Jason Te Bergendahl, Jason L
Phone and address:
262 Bentrup Ct, Lenox, MA 01240
(413) 637-1320
Connected to:
Albert L Bergendahl, 39Brett V Bergenfeld, 65Eric M Bergendahl, 33Julie A Bergendahl, 40Kamra M BergenerMary T Bergene, 75Melvin D Bergendale, 46Orland J Bergene, 86Scott A Bergener, 47Shasta P Bergener, 47

Jason Bergendahl Phones & Addresses

  • 262 Bentrup Ct, Lenox, MA 01240 (413) 637-1320
  • 37 Bentrup Ct, Lenox, MA 01240 (650) 377-3351
  • 10759 Juniper Ct, Cupertino, CA 95014 (408) 836-7722
  • Saratoga, CA
  • 1678 Lewiston Dr, Sunnyvale, CA 94087 (408) 377-3351
  • 1951 Ofarrell St, San Mateo, CA 94403
  • 1951 Ofarrell St #119, San Mateo, CA 94403
  • Campbell, CA
  • Somerville, MA
  • Santa Clara, CA

Work

Company: Intel corporation Dec 2017 Position: Engineering manager

Education

Degree: Masters, Master of Science In Electrical Engineering School / High School: Massachusetts Institute of Technology 1995 to 1997

Skills

Architecture • Verilog • Digital Design • Analog Circuit Design • Xilinx • Static Timing Analysis • Serdes • Engineering Management • Cross Functional Team Leadership • I/O • Ddr3 • Signal Integrity • Competitive Analysis • Altera • Fpga • Electrical Engineering • Hardware Architecture • Integrated Circuit Design • Simulations • Logic Synthesis • Xilinx Ise • Semiconductors • Cmos • Soc • Field Programmable Gate Arrays • System on A Chip

Languages

English

Industries

Semiconductors

Resumes

Resumes

Jason Bergendahl Photo 1

Engineering Manager

Location:
10759 Juniper Ct, Cupertino, CA 95014
Industry:
Semiconductors
Work:
Intel Corporation
Engineering Manager
Xilinx Aug 1997 - Dec 2017
Senior Staff Architect
Education:
Massachusetts Institute of Technology 1995 - 1997
Masters, Master of Science In Electrical Engineering University of Massachusetts Amherst 1991 - 1995
Bachelors, Bachelor of Science In Electrical Engineering Lenox Memorial High School
Skills:
Architecture
Verilog
Digital Design
Analog Circuit Design
Xilinx
Static Timing Analysis
Serdes
Engineering Management
Cross Functional Team Leadership
I/O
Ddr3
Signal Integrity
Competitive Analysis
Altera
Fpga
Electrical Engineering
Hardware Architecture
Integrated Circuit Design
Simulations
Logic Synthesis
Xilinx Ise
Semiconductors
Cmos
Soc
Field Programmable Gate Arrays
System on A Chip
Languages:
English

Publications

Us Patents

Digitally Controlled Impedance For I/O Of An Integrated Circuit Device

US Patent:
6489837, Dec 3, 2002
Filed:
Nov 30, 2001
Appl. No.:
10/007167
Inventors:
David P. Schultz - San Jose CA
Suresh M. Menon - Sunnyvale CA
Eunice Y. D. Hao - Saratoga CA
Jason R. Bergendahl - Campbell CA
Jian Tan - Milpitas CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G05F 110
US Classification:
327541, 327566, 36523003
Abstract:
A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.

Low Pass Filter

US Patent:
6559715, May 6, 2003
Filed:
Jul 18, 2000
Appl. No.:
09/618204
Inventors:
Scott O. Frake - Cupertino CA
Jason R. Bergendahl - Campbell CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 500
US Classification:
327558, 327552
Abstract:
A low pass filter (LPF) is provided that smoothes and significantly slows any change in its input voltage. The capacitance of the LPF is provided by an NMOS transistor having its source and drain tied to ground. The resistance of the LPF is provided by a plurality of series-connected PMOS transistors. The gates of the PMOS transistors are coupled to ground and therefore these transistors are conducting. The PMOS transistors are fabricated in a floating well. Therefore, the LPF eliminates any capacitive coupling between a voltage supply and the well. Thus, any variation in the supply voltage fails to affect adversely the functioning of the PMOS transistors. Thus, the LPF of the present invention can advantageously smooth and significantly slow any change in its input voltage. In one embodiment, the input voltage is a reference voltage. In this manner, a voltage regulator, which receives the filtered reference voltage from the LPF, in turn provides a significantly more constant regulated voltage to the internal circuits of the IC.

Methods For Aligning Data And Clock Signals

US Patent:
6798241, Sep 28, 2004
Filed:
Feb 27, 2003
Appl. No.:
10/376522
Inventors:
Trevor J. Bauer - Boulder CO
Steven P. Young - Boulder CO
Christopher D. Ebeling - San Jose CA
Jason R. Bergendahl - San Mateo CA
Arthur J. Behiel - Pleasanton CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19173
US Classification:
326 40, 326 93, 326 54, 326 37, 327115, 327117, 327276, 327156, 714700
Abstract:
Described are methods and circuits for aligning data and clock signals. Methods in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.

Windowing Circuit For Aligning Data And Clock Signals

US Patent:
6864715, Mar 8, 2005
Filed:
Feb 27, 2003
Appl. No.:
10/377461
Inventors:
Trevor J. Bauer - Boulder CO, US
Steven P. Young - Boulder CO, US
Christopher D. Ebeling - San Jose CA, US
Jason R. Bergendahl - San Mateo CA, US
Arthur J. Behiel - Pleasanton CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F007/38
H03K019/173
H03D003/24
US Classification:
326 46, 331 1 A, 375376
Abstract:
Described are circuits and methods for aligning data and clock signals. Circuits in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.

Bimodal Serial To Parallel Converter With Bitslip Controller

US Patent:
6985096, Jan 10, 2006
Filed:
Aug 17, 2004
Appl. No.:
10/919900
Inventors:
Paul T. Sasaki - Sunnyvale CA, US
Jason R. Bergendahl - Sunnyvale CA, US
Atul Ghia - San Jose CA, US
Jian Tan - Fremont CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03M 9/00
US Classification:
341100, 341101
Abstract:
Method and apparatus for a bimodal serial to parallel converter is provided. A first stage of registers is clocked responsive to a clock signal, such as a forwarded clock signal of a synchronous interface. The first stage of registers is configurable in either a single serial shift chain or two serial shift chains. The former configuration is for Single Data Rate (“SDR”) data, and the latter configuration is for Double Data Rate (“DDR”) data. A bitslip controller is configured to provide a control select signal to selection circuitry. For DDR operation, the control signal is for selecting respective portions of outputs from the two serial shift chains for providing to a second stage of registers. For DDR operation, the second stage of registers is alternatively clocked responsive to a divided down version of the clock signal and another divided down version of the clock signal which is periodically stopped.

Multi-Purpose Source Synchronous Interface Circuitry

US Patent:
7091890, Aug 15, 2006
Filed:
Aug 17, 2004
Appl. No.:
10/919901
Inventors:
Paul T. Sasaki - Sunnyvale CA, US
Jason R. Bergendahl - Sunnyvale CA, US
Atul Ghia - San Jose CA, US
Hassan Bazargan - San Jose CA, US
Ketan Sodha - Fremont CA, US
Jian Tan - Fremont CA, US
Qi Zhang - Milpitas CA, US
Suresh Menon - Sunnyvale CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03M 9/00
US Classification:
341100, 341 59
Abstract:
A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.

Clock Signal-Distribution Network For An Integrated Circuit

US Patent:
7145362, Dec 5, 2006
Filed:
Nov 5, 2004
Appl. No.:
10/981973
Inventors:
Jason R. Bergendahl - Sunnyvale CA, US
Ping-Chen Liu - Fremont CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19/00
US Classification:
326 47, 326 37, 326 41, 326 93
Abstract:
Apparatus for signal distribution, and more particularly to a clock-distribution network in an integrated circuit, is described. A programmable logic device includes an input buffer () and an input signal distribution buffer () coupled to the input buffer (). The input signal distribution buffer () is configured to distribute a clock signal () within an input/output block clock region (A, B). Signal lines (UD) extend to at least one other input signal distribution buffer ().

Regional Signal-Distribution Network For An Integrated Circuit

US Patent:
7353487, Apr 1, 2008
Filed:
Nov 5, 2004
Appl. No.:
10/981877
Inventors:
Jason R. Bergendahl - Sunnyvale CA, US
Ping-Chen Liu - Fremont CA, US
Paul T. Sasaki - Sunnyvale CA, US
Suresh M. Menon - Sunnyvale CA, US
Atul V. Ghia - San Jose CA, US
Steven P. Young - Boulder CO, US
Trevor J. Bauer - Boulder CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 17, 716 16, 716 18
Abstract:
Signal distribution of a regional signal is described. A programmable logic device includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.
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Jason R Bergendahl from Lenox, MA, age ~51 Get Report