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Eric N Lais

from Georgetown, TX
Age ~50
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Also known as:
Eric Norman Lais, Eric D Lais
Phone and address:
1120 Daylily Loop, Georgetown, TX 78626
Related to:
Billie L Nicolay, 46Donald D Hoyle, 83Desiree C Lais, 50Marcella L Procsal, 70Stephen S Procsal, 77Jean M Lais, 58Paula M Bandonis, 53Kevin D LaisMairead M Greenwell, 64
Connected to:
June A Lais, 63Kelly E Lais, 38Liliana X Lais, 48Sandra D Lais, 83Fisher Laishram, 39Renu Laishram, 51Brandy K Laisner, 51Amanda M Laister, 48Anthony LaisureRoxanne E Laisure, 69

Eric Lais Phones & Addresses

  • 1120 Daylily Loop, Georgetown, TX 78626
  • Austin, TX
  • 29 Colonial Dr, Tillson, NY 12486 (845) 658-7159 (845) 658-7335 (845) 658-7340
  • 6916 68Th Ave, Hillsboro, OR 97123 (503) 591-0629
  • Kingston, NY
  • Portland, OR
  • Eugene, OR
  • 29 Colonial Dr, Tillson, NY 12486

Work

Company: Ibm Jan 2000 Position: Hardware design engineer

Education

Degree: High school graduate or higher

Skills

Debugging • Hardware Architecture • Hardware • Perl • Pcie • Verilog • Testing • Vhdl • Computer Architecture • Linux • Embedded Systems • C • System Architecture • Embedded Software • Asic • Fpga

Emails

e***[email protected]

Industries

Computer Hardware

Resumes

Resumes

Eric Lais Photo 1

Hardware Design Engineer

Location:
Austin, TX
Industry:
Computer Hardware
Work:
Ibm
Hardware Design Engineer
Skills:
Debugging
Hardware Architecture
Hardware
Perl
Pcie
Verilog
Testing
Vhdl
Computer Architecture
Linux
Embedded Systems
C
System Architecture
Embedded Software
Asic
Fpga

Publications

Us Patents

Hazard Queue For Transaction Pipeline

US Patent:
6996665, Feb 7, 2006
Filed:
Dec 30, 2002
Appl. No.:
10/334427
Inventors:
Donald R. DeSota - Portland OR, US
Bruce M. Gilbert - Beaverton OR, US
Robert Joersz - Portland OR, US
Eric N. Lais - Tillson NY, US
Maged M. Michael - Danbury CT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
US Classification:
711109, 711108, 711140, 711169, 712216, 712217, 712218, 712219
Abstract:
A hazard queue for a pipeline, such as a multiple-stage pipeline for transaction conversion, is disclosed. A transaction in the pipeline is determined to represent a hazard relative to another transaction, such as by evaluating the transaction against a hazard content-addressable memory (CAM). The hazard CAM can enforce various hazard rules, such as considering a transaction as active if it is referencing a memory line and is currently being processed within the pipeline, and ensuring that only one active transaction with a given coherent memory line is in the pipeline at a single time. In response to determining that a transaction is a hazard, the transaction is routed to a hazard queue, such as at the end of the pipeline. Once the hazard is released, the transaction re-enters the pipeline.

Apparatus And Method For Decode Arbitration In A Multi-Stream Multimedia System

US Patent:
7035355, Apr 25, 2006
Filed:
Oct 4, 2001
Appl. No.:
09/971984
Inventors:
Eric Lais - Hillsboro OR, US
Mark Greenberg - Beaverton OR, US
Manish Shah - Beaverton OR, US
Assignee:
Digeo, Inc. - Kirkland WA
International Classification:
H03D 1/00
H04L 27/06
US Classification:
375341, 375260, 375262, 375265, 714792, 714794
Abstract:
An apparatus and method are described for mapping a plurality of multimedia streams (e. g. , received from a set of satellite transponders) across a lesser plurality of decoders. In one embodiment, arbitration logic allocates the multimedia streams to divide the decoding load equally among the group of decoders (or at least as equally as possible). Allocation may occur statically, when the system is initialized, or dynamically, as the streams are being processed. In addition, in one embodiment, the arbitration logic monitors the amount of multimedia data for each stream stored in a buffer and causes streams to be serviced by the decoders which have relatively more stored multimedia data.

Prefetch Miss Indicator For Cache Coherence Directory Misses On External Caches

US Patent:
7395375, Jul 1, 2008
Filed:
Nov 8, 2004
Appl. No.:
10/983350
Inventors:
Eric N. Lais - Tillson NY, US
Donald R. DeSota - Portland OR, US
Rob Joersz - Portland OR, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/08
US Classification:
711141, 711137, 711146
Abstract:
A system, method and article of manufacture for reducing latencies associated with cache coherence directory misses on external caches in a shared distributed memory data processing system. A cache coherence directory is evaluated for possible prefetching of a directory entry into a directory cache. A prefetch miss indicator is set if the prefetch evaluation results in a directory miss. The prefetch miss indicator is consulted during subsequent processing of a memory block request corresponding to the directory entry. An accelerated snoop response action is taken if the prefetch miss indicator is set. The latency of a second lookup into the cache coherence directory, which would otherwise be required, is thereby avoided.

Apparatus And Method For Decode Arbitration In A Multi-Stream Multimedia System

US Patent:
7440523, Oct 21, 2008
Filed:
Apr 24, 2006
Appl. No.:
11/409636
Inventors:
Eric Lais - Hillsboro OR, US
Mark Greenberg - Beaverton OR, US
Manish Shah - Beaverton OR, US
Assignee:
Digeo, Inc. - Kirkland WA
International Classification:
H03D 1/00
H04L 27/06
US Classification:
375341, 375260, 375262, 375265, 714792, 714794
Abstract:
An apparatus and method are described for mapping a plurality of multimedia streams (e. g. , received from a set of satellite transponders) across a lesser plurality of decoders. In one embodiment, arbitration logic allocates the multimedia streams to divide the decoding load equally among the group of decoders (or at least as equally as possible). Allocation may occur statically, when the system is initialized, or dynamically, as the streams are being processed. In addition, in one embodiment, the arbitration logic monitors the amount of multimedia data for each stream stored in a buffer and causes streams to be serviced by the decoders which have relatively more stored multimedia data.

Prefetch Miss Indicator For Cache Coherence Directory Misses On External Caches

US Patent:
7669010, Feb 23, 2010
Filed:
Apr 18, 2008
Appl. No.:
12/105405
Inventors:
Eric N. Lais - Tillson NY, US
Donald R. DeSota - Portland OR, US
Rob Joersz - Portland OR, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
US Classification:
711141, 365233, 370389, 709313, 711137, 711146, 714 5, 718103
Abstract:
A system, method and article of manufacture for reducing latencies associated with cache coherence directory misses on external caches in a shared distributed memory data processing system. A cache coherence directory is evaluated for possible prefetching of a directory entry into a directory cache. A prefetch miss indicator is set if the prefetch evaluated results in a directory miss. The prefetch miss indicator is consulted during subsequent processing of a memory block request corresponding to the directory entry. An accelerated snoop response action is taken if the prefetch miss indicator is set. The latency of a second lookup into the cache coherence directory, which would otherwise be required, is thereby avoided.

Memory Controller Having Tables Mapping Memory Addresses To Memory Modules

US Patent:
8250330, Aug 21, 2012
Filed:
Dec 11, 2004
Appl. No.:
11/010205
Inventors:
Eric N. Lais - Tillson NY, US
Donald R. DeSota - Portland OR, US
Michael Grassi - Shokan NY, US
Bruce M. Gilbert - Beaverton OR, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
G06F 13/00
G06F 13/28
G06F 12/06
G06F 9/26
G06F 9/34
G11C 8/00
US Classification:
711202, 36523005, 711205, 711206, 711207, 711 5, 711168, 711221, 711170
Abstract:
A memory controller includes ports and corresponding tables. Each port is receptive to one or more memory modules. Each table includes entries mapping memory addresses to the memory modules. Each entry corresponds to no more than one of the memory modules. The tables support asymmetric population of the memory modules within the ports; each port is capable of having a different number of memory modules relative to the other ports. The tables impose no restrictions on where the memory modules are to be inserted within the ports, both number-wise and position-wise. The tables are independently configurable; the configuration of each table is modifiable independently of the configurations of the other tables. Each table is dynamically configurable. The entries of a table are modifiable to reflect changes in the number and type of the memory modules connected, without restarting or temporarily halting the computer system containing the memory controller.

Selection Of A Domain Of A Configuration Access

US Patent:
8261128, Sep 4, 2012
Filed:
Aug 4, 2010
Appl. No.:
12/849925
Inventors:
Eric N. Lais - Tillson NY, US
Steve Thurber - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/00
US Classification:
714 43, 714 45, 714 51, 714 44, 714 56, 710306
Abstract:
A data processing system includes an input/output (I/O) host bridge to which at least one I/O adapter is coupled by an I/O link. In a register of the I/O host bridge, a configuration partitionable endpoint (PE) field is set to identify a PE to be used for an I/O configuration operation. Thereafter, the host bridge initiates the I/O configuration operation on the I/O link and determines if an error occurred for the I/O configuration operation. In response to a determination that an error occurred for the I/O configuration operation, an error state is set in the I/O host bridge only for the PE indicated in the configuration PE field of the register in the I/O host bridge, wherein I/O configuration errors are isolated to particular PEs.

Atomic Operations With Page Migration In Pcie

US Patent:
8407389, Mar 26, 2013
Filed:
Jul 20, 2010
Appl. No.:
12/839857
Inventors:
Eric Norman Lais - Poughkeepsie NY, US
Steve Thurber - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
G06F 13/36
G06F 13/28
US Classification:
710306, 710200, 710308, 711152
Abstract:
A method and data processing system enables scheduling of atomic operations within a Peripheral Component Interconnect Express (PCIe) architecture during page migration. In at least one embodiment, firmware detects the activation of a page migration operation. The firmware notifies the I/O host bridge, which responds by setting an atomic operation stall (AOS) bit to a pre-established value that indicates that there is an ongoing migration within the memory subsystem of a memory page that is mapped to that I/O host bridge. When the AOS bit is set to the pre-established value, the I/O host bridge prevents/stalls any received atomic operations from completing. The I/O host bridge responds to receipt of receipt of an atomic operation by preventing the atomic operation from being initiated within the memory subsystem, when the AOS bit is set to the pre-established value. The AOS bit is reset when the migration operation has completed.
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Eric N Lais from Georgetown, TX, age ~50 Get Report