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Dwight H Oda

from Rancho Palos Verdes, CA
Age ~60
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Also known as:
Dwight Hiroshi Oda, Dwight Hoda
Phone and address:
28856 Crestridge Rd, Palos Verdes Estates, CA 90275
(310) 541-9599
Related to:
Chad Koyanagi, 45Susumu S Koyanagi, 74Ingrid M Koyanagi, 72Steve KoyanagiNaomi Koyanagi, 71
Connected to:
Celeste V Oda, 62Chris Oda, 42Daniel T Oda, 34Dawn M Oda, 58Gail T Oda, 76Hiroko Oda, 58Kareem Oda, 35Katsumi Oda, 53Linda C Oda, 61Masakazu Oda, 77

Dwight Oda Phones & Addresses

  • 28856 Crestridge Rd, Rancho Palos Verdes, CA 90275 (310) 541-9599
  • Rch Palos Vrd, CA
  • Elkins Park, PA
  • Cypress, CA
  • Carson, CA
  • 16 Buenaventura, Rancho Santa Margarita, CA 92688 (949) 888-2691
  • Breedsville, MI
  • San Pedro, CA
  • Gardena, CA
  • Los Angeles, CA
  • Rch Palos Vrd, CA
  • 4569 Chantry Ct, Cypress, CA 90630 (949) 636-2521

Work

Position: Machine Operators, Assemblers, and Inspectors Occupations

Education

Degree: High school graduate or higher

Resumes

Resumes

Dwight Oda Photo 1

Dwight Oda

Location:
Greater Los Angeles Area
Industry:
Semiconductors
Dwight Oda Photo 2

Dwight Oda

Publications

Us Patents

Cross Link Multiplexer Bus

US Patent:
7450529, Nov 11, 2008
Filed:
Oct 29, 2003
Appl. No.:
10/695458
Inventors:
Abbas Amirichimeh - Irvine CA, US
Howard Baumer - Laguna Hills CA, US
Dwight Oda - Cypress CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04L 7/00
H04L 13/10
US Classification:
370304, 370299, 370300, 370301, 370307, 375353, 375355, 375356, 375357, 375359
Abstract:
A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce the signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. Preferably, the destination port is in a first cross link multiplexer, the origin port is in a second cross link multiplexer, and the first cross link multiplexer is configured to convey the signal toward the second cross link multiplexer in more than one direction. In an embodiment, the signal is capable of being represented as a series of characters, and a character is capable of being represented as a number of bits. Preferably, the plurality of cross link multiplexers includes a delay buffer to delay conveyance of a first bit so that it remains substantially synchronized with a second bit. Preferably, the set of interconnects includes a first interconnect to convey the first bit and a second interconnect to convey the second bit.

Cross Link Multiplexer Bus Configured To Reduce Cross-Talk

US Patent:
7450530, Nov 11, 2008
Filed:
Oct 29, 2003
Appl. No.:
10/695498
Inventors:
Abbas Amirichimeh - Irvine CA, US
Howard Baumer - Laguna Hills CA, US
Dwight Oda - Cypress CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04L 7/00
H04L 13/10
US Classification:
370304, 370299, 370300, 370301, 370307, 375355, 375353, 375356, 375357, 375359
Abstract:
A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce said signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. The signal is capable of being represented as a series of characters. A character is capable of being represented as a first data bit, a second data bit, and a control bit. A first interconnect is configured to convey the first data bit. A second interconnect is configured to convey the second data bit. A third interconnect is configured to convey the control bit. The third interconnect is positioned substantially between the first interconnect and the second interconnect.

Electronic Shark Deterrent

US Patent:
7924165, Apr 12, 2011
Filed:
Sep 25, 2008
Appl. No.:
12/238185
Inventors:
Wilson Vinano, Jr. - Honolulu HI, US
Calvin Maeda - Honolulu HI, US
Gary Maeda - Torrance CA, US
Dwight Oda - Rancho Palos Verdes CA, US
Assignee:
ZTOA Innovations, LLC - Honolulu HI
International Classification:
G08B 23/00
US Classification:
3405733, 119219, 119720, 119220, 340540
Abstract:
An Electronic Shark Deterrent provides protection from, and for, sharks and other aquatic creatures. Compact low power circuitry generates high voltage periodic pulse train bursts, disturbing the electroreceptors of the aquatic Elasmobranchi subclass. A train of thirty 33 us 250 Volt (V) electric pulses lasting one second is produced every six seconds. The device is fully portable, requiring no bulky activity impeding buoys, cords, or external power supplies. Advanced circuitry is compact enough to be worn on a watch sized band or attached to garments and recreation or safety equipment. The deterrent can be used in a fixed configuration to protect fish farms and vacation resort swimming areas. It can be affixed to offshore oil rigs and research stations to protect workers. The Electronic Shark Deterrent is compact and portable enough to be used on longlines, trawls and gillnets to reduce the numbers of endangered aquatic creatures unnecessarily destroyed as bycatch.

Cross Link Multiplexer Bus

US Patent:
8094590, Jan 10, 2012
Filed:
Oct 17, 2008
Appl. No.:
12/253851
Inventors:
Abbas Amirichimeh - Irvine CA, US
Howard Baumer - Laguna Hills CA, US
Dwight Oda - Cypress CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04L 13/10
US Classification:
370304
Abstract:
A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce the signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. Preferably, the destination port is in a first cross link multiplexer, the origin port is in a second cross link multiplexer, and the first cross link multiplexer is configured to convey the signal toward the second cross link multiplexer in more than one direction. In an embodiment, the signal is capable of being represented as a series of characters, and a character is capable of being represented as a number of bits. Preferably, the plurality of cross link multiplexers includes a delay buffer to delay conveyance of a first bit so that it remains substantially synchronized with a second bit. Preferably, the set of interconnects includes a first interconnect to convey the first bit and a second interconnect to convey the second bit.

High-Speed Data Register For Laser Range Finders

US Patent:
56443870, Jul 1, 1997
Filed:
Jun 7, 1995
Appl. No.:
8/484736
Inventors:
Dwight N. Oda - Rancho Santa Margarita CA
Gregson D. Chinn - Oro Valley AZ
Charles E. Nourrcier - Lakewood CA
Assignee:
Hughes Electronics - Los Angeles CA
International Classification:
G01C 308
G11C 1900
US Classification:
356 501
Abstract:
A high-speed data register for storing a series of data values received at a high-speed clock rate and including a first set of pipelined latches and a second set of pipelined latches. Control circuitry loads the received data values alternately into said first set of latches and said second set of latches from an input or "last" register, which stores the last data value received by the data register. Data values thus enter the last register at the high-speed clock rate but are loaded into each of the first and second set of pipelined latches at one-half that rate.

High-Speed Synchronous Counter Circuitry

US Patent:
59433868, Aug 24, 1999
Filed:
May 24, 1995
Appl. No.:
8/449461
Inventors:
Gregson D. Chinn - Oro Valley AZ
Dwight N. Oda - Rancho Santa Margarita CA
Assignee:
Hughes Electronics - Los Angeles CA
International Classification:
H03K 2116
US Classification:
377116
Abstract:
Digital counter register stages are constructed as two-to-one mux registers, each employing a multiplexer stage having first, second, and third inputs and an output connected to the switching signal input of a D-type flip-flop, whose Q output comprises a first input to the multiplexer stage. An inverter buffer is associated with each register stage and has an input connected to the output of said D-type flip-flop and an output connected to the second input of the multiplexer stage and fed forward to a NOR gate associated with each subsequent register stage. The output of the NOR gate comprises the third input to the multiplexer stage of the associated register stage.
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Dwight H Oda from Rancho Palos Verdes, CA, age ~60 Get Report