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Dixie Dunn Phones & Addresses

  • Sunnyvale, CA
  • 861 Apricot Ave, Campbell, CA 95008
  • San Jose, CA
  • 1459 S Yuma St, Salt Lake City, UT 84108 (801) 461-0801 (801) 755-4348
  • 1517 Lincoln St, Salt Lake City, UT 84105 (801) 461-0801
  • Holladay, UT
  • Tremonton, UT

Resumes

Resumes

Dixie Dunn Photo 1

Senior Vice President Customer Advocacy | Enterprise Software | Aiops | Big Data | Ml And Ai

Location:
861 Apricot Ave, Campbell, CA 95008
Industry:
Computer Software
Work:
Fairchild Semiconductor - San Jose, CA since Nov 2009
Product and Test Engineering Manager

Fairchild Semiconductor Oct 2000 - Nov 2009
Staff Engineer New Product Introduction

WesTech Engineering 1993 - 2000
Lab Manager
Education:
University of Utah - David Eccles School of Business 2005 - 2007
Executive MBA
University of Utah 1993 - 1996
Bachelors, Physics
Skills:
Semiconductors
Product Engineering
Semiconductor Industry
Manufacturing
Ic
Spc
Product Development
Design of Experiments
Test Engineering
Six Sigma
Failure Analysis
Analog
Yield
Engineering
Silicon
Jmp
Process Engineering
Cmos
R&D
Lean Manufacturing
Statistics
Statistical Process Control
Risk Analysis
Research and Development
Device Characterization
Startup
Customer Relationship Management
Program Management
Strategy
Interests:
Poverty Alleviation
Science and Technology
Languages:
English
Certifications:
Six Sigma Black Belt Certification By Sigma Breakthrough Technologies
Dixie Dunn Photo 2

Owner

Work:
Be Dazzled By Dixie
Owner
Skills:
Social Media
Jewelry
New Business Development
Strategic Planning
Marketing Strategy
Social Media Marketing
Sales Management
Sales
Event Management
Team Building
Advertising
Dixie Dunn Photo 3

Dixie Dunn

Dixie Dunn Photo 4

Dixie Dunn

Publications

Us Patents

Shield Contacts In A Shielded Gate Mosfet

US Patent:
8338285, Dec 25, 2012
Filed:
May 9, 2011
Appl. No.:
13/104006
Inventors:
Dixie Dunn - Salt Lake City UT, US
Paul Thorup - West Jordan UT, US
Dean E. Probst - West Jordan UT, US
Michael D. Gruenhagen - Salt Lake City UT, US
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 21/28
US Classification:
438589, 257334
Abstract:
A semiconductor structure is formed as follows. Trenches are formed in a semiconductor region and a shield electrode is formed in each trench. Gate electrodes are formed in a portion of the trenches that form an active region. Each gate electrode is disposed over the shield electrode and is isolated from the shield electrode by an inter-electrode dielectric. An interconnect layer is formed extending over the trenches. The interconnect layer is isolated from the gate electrodes in the active region by a dielectric layer and contacts the shield electrodes in a shield contact region separate from the active region. The interconnect layer contacts mesa surfaces between adjacent trenches in the shield contact region.

Shield Contacts In A Shielded Gate Mosfet

US Patent:
20110018059, Jan 27, 2011
Filed:
Jul 24, 2009
Appl. No.:
12/509379
Inventors:
Dixie Dunn - Salt Lake City UT, US
Paul Thorup - West Jordan UT, US
Dean E. Probst - West Jordan UT, US
Michael D. Gruenhagen - Salt Lake City UT, US
International Classification:
H01L 29/78
H01L 21/28
US Classification:
257334, 438586, 257E29262, 257E2119
Abstract:
A semiconductor structure comprises an active region comprising trenches extending into a semiconductor region. Each trench includes a shield electrode and a gate electrode. The semiconductor structure also comprises a shield contact region adjacent to the active region. The shield contact region comprises at least one contact trench extending into the semiconductor region. The shield electrode from at least one of the trenches in the active region extends along a length of the contact trench. The semiconductor structure also comprises an interconnect layer extending over the active region and the shield contact region. In the active region the interconnect layer is isolated from the gate electrode in each trench by a dielectric layer and contacts mesa surfaces of the semiconductor region adjacent to the trenches. In the shield contact region the interconnect layer contacts the shield electrode and the mesa surfaces of the semiconductor region adjacent to the contact trench.

Low Temperature Microwave Activation Of Heavy Body Implants

US Patent:
20120034769, Feb 9, 2012
Filed:
Aug 5, 2011
Appl. No.:
13/204017
Inventors:
Robert J. Purtell - West Jordan UT, US
Dixie Dunn - Salt Lake City UT, US
International Classification:
H01L 21/265
US Classification:
438530, 257E21334
Abstract:
Semiconductor devices and methods for making such devices are described. The semiconductor devices contain dopant regions that have been formed by low temperature, microwave activation of implanted dopants. In some configurations, the low temperature microwave activation can be used to control the final location of the implant, with or without additional drive-in or implant processes. In some configurations, this control can be used to create heavy body implants. Microwave activation of source regions and well regions in the semiconductor devices can also be used to optimize the implants where supplemental drive-in processes may be necessary to get the required final implant depth. By activating the implanted dopants using lower temperatures, many of the unwanted features introduced into the semiconductor devices by high temperature Rapid Thermal Process (RTP) can be avoided. Other embodiments are described.

Wikipedia

Delta Air Lines Flight 1141

Flight Attendants Dixie Dunn and Rosilyn Marr and passengers Millar Browne, 55 ; Glen Campbell, 54; Jennifer Campbell, 44; Marian Fadal, 65; Barbara Morgan ...

Dixie L Dunn from Sunnyvale, CA, age ~51 Get Report