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Deepak Ganapathy Phones & Addresses

  • 124 Cobble Ridge Dr, Folsom, CA 95630 (916) 608-8842
  • 9237 Greenback Ln, Orangevale, CA 95662
  • 936 S Terrace Rd, Tempe, AZ 85281 (480) 829-0074
  • Sacramento, CA

Work

Position: Sales Occupations

Education

Degree: High school graduate or higher

Resumes

Resumes

Deepak Ganapathy Photo 1

Smartphone Thermal Management Engineer At Intel Corporation

Location:
124 Cobble Ridge Dr, Folsom, CA 95630
Industry:
Semiconductors
Work:
Intel Corporation Jul 2009 - Jun 2012
Thermal Engineering Manager

Intel Corporation Jul 2009 - Jun 2012
Smartphone Thermal Management Engineer at Intel Corporation

Intel Corporation Sep 2007 - Jul 2009
Thermal Team Technical Lead

Intel Corporation Sep 2005 - Sep 2007
Thermal Packaging Engineer

Intel Corporation Jan 2005 - Sep 2005
Thermal Packaging Intern
Education:
Arizona State University 2002 - 2004
Master of Science, Masters, Mechanical Engineering
University of Madras 1998 - 2002
Bachelor of Engineering, Bachelors, Mechanical Engineering
Arizona State University 1976 - 1980
Master of Science, Masters
Skills:
Semiconductors
Labview
Matlab
Simulations
Engineering
Icepak
Jmp
Physics
Thin Films
Thermal
Cfd
Cad
Management
Manufacturing
Design of Experiments
C++
C
Flotherm
Ansys
Visual Basic
Visio
Mathematica
Minitab
Numerical Analysis
Microsoft Excel
Data Analysis
Managerial Experience
Excel
Languages:
English
Tamil
Hindi
Telugu
Deepak Ganapathy Photo 2

Deepak Ganapathy

Publications

Us Patents

Dynamic Energy Performance Preference Based On Workloads Using An Adaptive Algorithm

US Patent:
20220187893, Jun 16, 2022
Filed:
Jul 14, 2020
Appl. No.:
17/442374
Inventors:
- Santa Clara CA, US
Efraim ROTEM - Haifa, IL
Eliezer WEISSMANN - Haifa, IL
Hisham ABU SALAH - Majdal Shams, IL
Hadas BEJA - Yahud, IL
Russell FENGER - Beaverton OR, US
Deepak GANAPATHY - Folsom CA, US
James HERMERDING, II - Vancouver WA, US
Ido KARAVANY - Givot Bar, IL
Nivedha KRISHNAKUMAR - Bangalore, IN
Sudheer NAIR - Portland OR, US
Gilad OLSWANG - Kfar Menahem, IL
Moran PERI - Kiryat Mtotzkin, IL
Avishai WAGNER - Kfar Sabe, IL
Zhongsheng WANG - Portland OR, US
Noha YASSIN - Arraba, IL
International Classification:
G06F 1/324
G06F 1/3296
Abstract:
Described are mechanisms and methods for tracking user behavior profile over large time intervals and extracting observations for a user usage profile. The mechanisms and methods use machine learning (ML) algorithms embedded into a dynamic platform and thermal framework (DPTF) (e.g., Dynamic Tuning Technology) and predict device workloads using hardware (HW) counters. These mechanisms and methods may accordingly increase performance and user responsiveness by dynamically changing an Energy Performance Preference (EPP) based on a longer time workload analysis and workload prediction.

Generation Of Processor Interrupts Using Averaged Data

US Patent:
20200264996, Aug 20, 2020
Filed:
May 7, 2020
Appl. No.:
16/868603
Inventors:
- Santa Clara CA, US
JEREMY J. SHRALL - Portland OR, US
DEEPAK GANAPATHY - Folsom CA, US
DORIT SHAPIRA - Atlit, IL
International Classification:
G06F 13/24
G06F 1/3234
G06F 1/20
G06F 1/3296
Abstract:
In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.

Generation Of Processor Interrupts Using Averaged Data

US Patent:
20180095913, Apr 5, 2018
Filed:
Sep 30, 2016
Appl. No.:
15/281472
Inventors:
- Santa Clara CA, US
JEREMY J. SHRALL - Portland OR, US
DEEPAK GANAPATHY - Folsom CA, US
DORIT SHAPIRA - Atlit, IL
International Classification:
G06F 13/24
G06F 1/32
G06F 1/20
Abstract:
In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.
Deepak Ganapathy from Folsom, CA, age ~43 Get Report