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Chuan-Cheng C Cheng

from San Diego, CA
Age ~55
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Related to:
Hung Min Jen, 53Yan Wang, 34Sha Chang, 39Limin Feng, 58Hung W Hung, 54Shih C Chen, 56Hui S Sieber, 65Chen Yang
Connected to:
An K Cheng, 52Anbay Cheng, 45Bon C Cheng, 43Bun Cheng, 56Cat F Cheng, 75Celina S Cheng, 46Chao Y Cheng, 73Cheung B Cheng, 76Chou L Cheng, 55Christy Cheng, 65

Chuan-Cheng Cheng Phones & Addresses

  • 6170 African Holly Trl, San Diego, CA 92130 (530) 519-0638
  • Fremont, CA

Resumes

Resumes

Chuan-Cheng Cheng Photo 1

Chuan-Cheng Cheng

Location:
San Diego, CA
Industry:
Semiconductors
Work:
Marvell
Sr. Technical Manager
Education:
California Institute of Technology 1993 - 1998
Chuan-Cheng Cheng Photo 2

Chuan-Cheng Cheng

Work:
Qualcomm 2014 - 2015
Principal Engineer

Publications

Us Patents

Integrated Capacitor And Fuse

US Patent:
6627968, Sep 30, 2003
Filed:
Oct 25, 2002
Appl. No.:
10/280567
Inventors:
Chuan-Cheng Cheng - Fremont CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 2900
US Classification:
257529, 257528, 257532, 257209
Abstract:
A process for forming a capacitive structure and a fuse structure in an integrated circuit device includes forming a first capacitor plate and first and second fuse electrodes in a first dielectric layer of the device. In a second dielectric layer overlying the first dielectric layer, a capacitor dielectric section overlying the first capacitor plate, and a fuse barrier section overlying and between the first and second fuse electrodes are formed simultaneously. In a conductive layer overlying the second dielectric layer, a second capacitor plate overlying the capacitor dielectric section, and a fuse overlying the fuse barrier section and contacting the first and second fuse electrodes are formed simultaneously. The capacitor dielectric section and the fuse barrier section may be defined simultaneously by selectively removing portions of the first dielectric layer during a single etching step. The second capacitor plate and the fuse may be defined simultaneously by selectively removing portions of the conductive layer during a single etching step.

Low Resistance Metal Interconnect Lines And A Process For Fabricating Them

US Patent:
6815342, Nov 9, 2004
Filed:
Nov 27, 2001
Appl. No.:
09/996118
Inventors:
Chuan-cheng Cheng - Fremont CA
Sethuraman Lakshminarayanan - San Jose CA
Peter J. Wright - Sunnyvale CA
Hong Ying - San Jose CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 214763
US Classification:
438648, 438657, 438687, 438688
Abstract:
Low resistance interconnect lines and methods for fabricating them are described herein. IC fabrication processes are used to create interconnect lines of Al and Cu layers. The Cu layer is thinner than in the known art, but in combination with the Al layer, the aggregate Cu/Al resistance is lowered to a point where it is comparable to that of a very thick Cu layer, without the additional cost and yield problems caused by using a thicker Cu deposition. Fuses for memory repair can also be fabricated using the methods taught by the present invention with only small variations in the process.

Fuse Structures, Methods Of Making And Using The Same, And Integrated Circuits Including The Same

US Patent:
6940107, Sep 6, 2005
Filed:
Dec 12, 2003
Appl. No.:
10/734779
Inventors:
Chuan-Cheng Cheng - Fremont CA, US
Shuhua Yu - Cupertino CA, US
Roawen Chen - San Jose CA, US
Albert Wu - Palo Alto CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H01L027/10
US Classification:
257209, 257529, 257530
Abstract:
A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

Fuse Structures, Methods Of Making And Using The Same, And Integrated Circuits Including The Same

US Patent:
7344924, Mar 18, 2008
Filed:
May 24, 2005
Appl. No.:
11/136925
Inventors:
Chuan-Cheng Cheng - Fremont CA, US
Shuhua Yu - Cupertino CA, US
Roawen Chen - San Jose CA, US
Albert Wu - Palo Alto CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H01L 21/82
US Classification:
438129, 438132, 438215, 257209
Abstract:
A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

Fuse Structures, Methods Of Making And Using The Same, And Integrated Circuits Including The Same

US Patent:
7589363, Sep 15, 2009
Filed:
May 22, 2007
Appl. No.:
11/805290
Inventors:
Chuan-Cheng Cheng - Fremont CA, US
Shuhua Yu - Cupertino CA, US
Roawen Chen - San Jose CA, US
Albert Wu - Palo Alto CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H01L 27/10
H01L 29/00
US Classification:
257209, 257529, 257530, 438129
Abstract:
A structure configured to disconnect circuit elements. The structure generally includes a dielectric layer over a light-absorbing structure, and a lens over the dielectric layer and the light-absorbing structure, configured to at least partially focus light onto the light-absorbing structure. The light-absorbing structure absorbs a first wavelength of light with a minimum threshold efficiency, the lens is substantially opaque to the first wavelength of light, and the dielectric layer is substantially transparent to the first wavelength of light. The structure advantageously provides improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

Fuse Structures, Methods Of Making And Using The Same, And Integrated Circuits Including The Same

US Patent:
7704805, Apr 27, 2010
Filed:
Feb 4, 2008
Appl. No.:
12/012723
Inventors:
Chuan-Cheng Cheng - Fremont CA, US
Shuhua Yu - Cupertino CA, US
Roawen Chen - San Jose CA, US
Albert Wu - Palo Alto CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H01L 21/82
H01L 21/8238
H01L 21/336
US Classification:
438132, 438129, 438215, 438281
Abstract:
A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

Integrated Circuit Devices With Esd And I/O Protection

US Patent:
7808075, Oct 5, 2010
Filed:
Aug 16, 2006
Appl. No.:
11/505782
Inventors:
Chuan-Cheng Cheng - Fremont CA, US
Choy Hing Li - Saratoga CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H01L 23/58
US Classification:
257528, 257724, 257777
Abstract:
The integrated circuit devices disclosed herein generally include two semiconductor dies. The first die generally has little or no I/O or ESD protection and includes a first plurality of exposed terminals (e. g. , bump pads). The second die generally includes (i) a second plurality of exposed terminals, wherein at least one of the second plurality of terminals is in electrical communication with one or more of the first plurality of terminals, (ii) a plurality of input and/or output (I/O) circuits, wherein at least one of the I/O circuits is in electrical communication with one or more of the second plurality of terminals, and (iii) a plurality of I/O terminals, wherein at least one of the I/O terminals is in electrical communication with one or more of the I/O circuits. The present invention advantageously provides the ability to fabricate the second die using different (e. g. , less expensive) manufacturing processes than those used to fabricate the first die.

Methods Of Making And Using Fuse Structures, And Integrated Circuits Including The Same

US Patent:
7820493, Oct 26, 2010
Filed:
Feb 4, 2008
Appl. No.:
12/012724
Inventors:
Chuan-Cheng Cheng - Fremont CA, US
Shuhua Yu - Cupertino CA, US
Roawen Chen - San Jose CA, US
Albert Wu - Palo Alto CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H01L 27/10
H01L 21/8239
US Classification:
438132, 438129, 438215, 438281, 438601, 257209, 257529, 257E2315
Abstract:
A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).
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Chuan-Cheng C Cheng from San Diego, CA, age ~55 Get Report