Search

Ashok M Khathuria

from San Jose, CA
Age ~72
Get Report
Also known as:
Ashok M Kathuria, Ashok Khajuria, Ashok A
Phone and address:
5512 Castle Glen Ave, San Jose, CA 95129
(408) 973-1673
Related to:
Ramesh Mulchand Khathuria, 75Thongbai YoderJustin J Williams, 39Thongbai T Yoder, 74Naresh M Khathuria, 67Monica A Khathuria, 65Rachel A Khathuria, 38Robert Yoder Rummy, 54Kapil A Khathuria, 40
Connected to:
Rajesh K Khati, 51Abdel G Khatib, 63Abeer N Khatib, 62Ahmad M Khatib, 60Amani A Khatib, 36Arif Khatib, 90Dina M Khatib, 34Jamal A Khatib, 65Jessica L Khatib, 30Kacey E Khatib, 37

Ashok Khathuria Phones & Addresses

  • 5512 Castle Glen Ave, San Jose, CA 95129 (408) 973-1673 (408) 691-9160
  • Morgan Hill, CA

Resumes

Resumes

Ashok Khathuria Photo 1

Owner

Location:
San Jose, CA
Industry:
Semiconductors
Work:
Actively seeking employment as a Program/Project Manager since Sep 2011
Program/Project Manager for Manufacturing, Merchandise, or Service Company
Solyndra, Inc Aug 2010 - Aug 2011
Sr. Process Engineer
Spansion LLC Mar 2005 - Mar 2009
Sr. Process/Equipment Lead Engineer (Sr.Member of Technical Staff)
Spansion LLC Mar 2002 - Mar 2005
Sr. Process/Equipment Engineer (Member of Technical Staff)
Advanced Micro Devices Mar 1992 - Mar 2002
Sr. Process/Equipment Sustaining Engineer
Education:
San Jose State University 1990 - 1993
MS, Engineering
Skills:
Poly and Dielectric Dry Plasma Etch Process
Metrology Equipment
Cigs
Lam2300 Poly Etch
Oxide Etch
Problem Solving
Project Management
Design of Experiments
Plasma Etch
Spc
Semiconductors
Metrology
Managerial Accounting
Leadership Technique
Process Integration
Process Engineering
Manufacturing
Program Management
Cross Functional Team Leadership
Silicon
Yield
Thin Films
Semiconductor Industry
R&D
Characterization
Failure Analysis
Engineering
Testing
Fmea
Lithography
Plasma Physics
Languages:
English
Ashok Khathuria Photo 2

Semiconductor Process Engineering Professional

Position:
Program/Project Manager for Manufacturing, Merchandise, or Service Company at Actively seeking employment as a Program/Project Manager (Self-employed)
Location:
San Jose, California
Industry:
Semiconductors
Work:
Actively seeking employment as a Program/Project Manager since Sep 2011
Program/Project Manager for Manufacturing, Merchandise, or Service Company
Solyndra, Inc Aug 2010 - Aug 2011
Sr. Process Engineer
Spansion LLC Mar 2005 - Mar 2009
Sr. Process/Equipment Lead Engineer (Sr.Member of Technical Staff)
Spansion LLC Mar 2002 - Mar 2005
Sr. Process/Equipment Engineer (Member of Technical Staff)
Advanced Micro Devices Mar 1992 - Mar 2002
Sr. Process/Equipment Sustaining Engineer
Education:
San Jose State University 1990 - 1993
MS, Engineering
Skills:
Poly & Dielectric Dry Plasma Etch Process
Metrology Equipment
CIGS
LAM2300 Poly Etch
AMAT MxP, MxP+
Oxide Etch
Problem Solving
Project Management
Design of Experiments
Plasma Etch
SPC
Semiconductors
Metrology
Managerial Accounting
Leadership Technique
Process Integration

Publications

Us Patents

Polymer Memory Device Formed In Via Opening

US Patent:
6787458, Sep 7, 2004
Filed:
Jul 7, 2003
Appl. No.:
10/614397
Inventors:
Nicholas H. Tripsas - San Jose CA
Matthew S. Buynoski - Palo Alto CA
Suzette K. Pangrle - Cupertino CA
Uzodinma Okoroanyanwu - Mountain View CA
Angela T. Hui - Fremont CA
Christopher F. Lyons - Fremont CA
Ramkumar Subramanian - Sunnyvale CA
Sergey D. Lopatin - Santa Clara CA
Minh Van Ngo - Fremont CA
Ashok M. Khathuria - San Jose CA
Mark S. Chang - Los Altos CA
Patrick K. Cheung - Sunnyvale CA
Jane V. Oglesby - Mountain View CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2144
US Classification:
438652, 438618, 438629, 438637, 438672, 438687, 438780, 438 99
Abstract:
One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.

Silicon Containing Material For Patterning Polymeric Memory Element

US Patent:
6803267, Oct 12, 2004
Filed:
Jul 7, 2003
Appl. No.:
10/614484
Inventors:
Ramkumar Subramanian - Sunnyvale CA
Christopher F. Lyons - Fremont CA
Matthew S. Buynoski - Palo Alto CA
Patrick K. Cheung - Sunnyvale CA
Angela T. Hui - Fremont CA
Ashok M. Khathuria - San Jose CA
Sergey D. Lopatin - Santa Clara CA
Minh Van Ngo - Fremont CA
Jane V. Oglesby - Mountain View CA
Terence C. Tong - Sunnyvale CA
James J. Xie - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21336
US Classification:
438197, 438706
Abstract:
The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.

Enhanced Transistor Gate Using E-Beam Radiation

US Patent:
6828259, Dec 7, 2004
Filed:
Dec 14, 2001
Appl. No.:
10/017855
Inventors:
Philip A. Fisher - Foster City CA
Marina V. Plat - San Jose CA
Russell R.A. Callahan - San Jose CA
Ashok M. Khathuria - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2126
US Classification:
438795, 438671, 438720, 438723, 438719, 430328, 430313, 430296
Abstract:
A process for forming a transistor having a gate width of less than 70 nm is disclosed herein. The process includes E-beam irradiation a gate patterned on a photoresist layer, trimming the gate patterned on the photoresist layer, and etching the gate patterned on the photoresist layer to a polysilicon layer disposed below the photoresist layer.

System And Method Of Forming A Passive Layer By A Cmp Process

US Patent:
6836398, Dec 28, 2004
Filed:
Oct 31, 2002
Appl. No.:
10/284769
Inventors:
Ramkumar Subramanian - Sunnyvale CA
Jane V. Oglesby - Mountain View CA
Minh Van Ngo - Fremont CA
Mark S. Chang - Los Altos CA
Sergey D. Lopatin - Santa Clara CA
Angela T. Hui - Fremont CA
Christopher F. Lyons - Fremont CA
Patrick K. Cheung - Sunnyvale CA
Ashok M. Khathuria - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01G 435
US Classification:
361302, 361303, 361305, 3613211, 3613215, 361311, 361313, 257529, 257532
Abstract:
The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing chemistry that forms the passive layer in a dish region of an electrode. Thus, the passive layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.

Hard Mask Spacer For Sublithographic Bitline

US Patent:
6962849, Nov 8, 2005
Filed:
Dec 5, 2003
Appl. No.:
10/729732
Inventors:
Tazrien Kamal - San Jose CA, US
Weidong Qian - Sunnyvale CA, US
Kouros Ghandehari - Santa Clara CA, US
Taraneh Jamali-Beh - Santa Cruz CA, US
Mark T. Ramsbey - Sunnyvale CA, US
Ashok M. Khathuria - San Jose CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L021/336
US Classification:
438257
Abstract:
A technique for forming at least part of an array of a dual bit memory core is disclosed. Spacers are utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e. g. , narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e. g. , for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.

Method For Reducing Resist Height Erosion In A Gate Etch Process

US Patent:
7005386, Feb 28, 2006
Filed:
Sep 5, 2003
Appl. No.:
10/656467
Inventors:
Scott Bell - San Jose CA, US
Ashok M. Khathuria - San Jose CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21/302
US Classification:
438709, 438714, 438724, 438725
Abstract:
According to one exemplary embodiment, a method for reducing resist height erosion in a gate etch process comprises a step of forming a first resist mask on an anti-reflective coating layer situated over a substrate, where the first resist mask has a first width. The anti-reflective coating layer may be, for example, an organic material. The method further comprises a step of trimming the first resist mask to form a second resist mask, where the second resist mask has a second width, and where the second width is less than the first width. The step of trimming the first resist mask may further comprise, for example, etching the anti-reflective coating layer. According to this exemplary embodiment, the method further comprises a step of performing an HBr plasma treatment on the second resist mask, wherein the HBr plasma treatment causes a vertical etch rate of the second resist mask to decrease.

Self Aligned Memory Element And Wordline

US Patent:
7220985, May 22, 2007
Filed:
Dec 9, 2002
Appl. No.:
10/314591
Inventors:
Patrick K. Cheung - Sunnyvale CA, US
Ashok M. Khathuria - San Jose CA, US
Assignee:
Spansion, LLC - Sunnyvale CA
International Classification:
H01L 21/00
H01L 29/08
H01L 35/24
H01L 51/00
US Classification:
257 40, 438 82
Abstract:
An organic polymer memory cell is provided having an organic polymer layer and an electrode layer formed over a first conductive (e. g. , copper) layer (e. g. , bitline). The memory cells are connected to a second conductive layer (e. g. , forming a wordline), and more particularly the top of the electrode layer of the memory cells to the second conductive layer. Optionally, a conductivity facilitating layer is formed over the conductive layer. Dielectric material separates the memory cells. The memory cells are self-aligned with the bitlines formed in the first conductive layer and the wordlines formed in the second conductive layer.

Self Aligned Memory Element And Wordline

US Patent:
7645632, Jan 12, 2010
Filed:
May 18, 2007
Appl. No.:
11/750724
Inventors:
Patrick K. Cheung - Sunnyvale CA, US
Ashok M. Khathuria - San Jose CA, US
Assignee:
Spansion LLC - Sunnyvale CA
International Classification:
H01L 51/40
US Classification:
438 99, 257 40
Abstract:
An organic polymer memory cell is provided having an organic polymer layer and an electrode layer formed over a first conductive (e. g. , copper) layer (e. g. , bitline). The memory cells are connected to a second conductive layer (e. g. , forming a wordline), and more particularly the top of the electrode layer of the memory cells to the second conductive layer. Optionally, a conductivity facilitating layer is formed over the conductive layer. Dielectric material separates the memory cells. The memory cells are self-aligned with the bitlines formed in the first conductive layer and the wordlines formed in the second conductive layer.
Control profile
Ashok M Khathuria from San Jose, CA, age ~72 Get Report