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Han B Chou

from Santa Clara, CA
Age ~49

Han Chou Phones & Addresses

  • 1803 Henning Pl, Santa Clara, CA 95050
  • San Ramon, CA
  • Union City, CA
  • 28 Fenway, Boston, MA 02215 (617) 262-3529
  • Foster City, CA
  • San Jose, CA
  • Alameda, CA
  • 4049 Crandall Cir, Santa Clara, CA 95054

Work

Position: Professional/Technical

Resumes

Resumes

Han Chou Photo 1

Csm, Pmp, Project/Program Management/Pmo

Location:
San Francisco Bay Area
Industry:
Information Technology and Services
Han Chou Photo 2

Manager, Asic Design Audio And Video

Location:
Santa Clara, CA
Industry:
Semiconductors
Work:
Nvidia Dec 2006 - Oct 2011
Senior Asic Designer

Nvidia Dec 2006 - Oct 2011
Manager, Asic Design Audio and Video

Portalplayer, Inc. Oct 2004 - Dec 2006
Senior Asic Designer

Nvidia Jan 2003 - Oct 2004
Asic Designer

Fast-Chip Aug 1999 - Jan 2003
Asic Designer
Education:
Massachusetts Institute of Technology Sep 1993 - 1998
Masters, Master of Engineering, Electrical Engineering, Computer Science, Engineering
Skills:
Asic
Rtl Design
Soc
Microarchitecture
Verilog
Management
Project Management
Han Chou Photo 3

Han Chou

Location:
United States
Han Chou Photo 4

Pmo Manager At Esc

Location:
San Francisco Bay Area
Industry:
Transportation/Trucking/Railroad
Han Chou Photo 5

Han Chou

Publications

Us Patents

Method And Circuit For Efficient Caching Of Reference Video Data

US Patent:
8593469, Nov 26, 2013
Filed:
Mar 29, 2006
Appl. No.:
11/391861
Inventors:
Parthasarathy Sriram - Los Altos CA, US
Han Chou - Santa Clara CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06T 15/00
US Classification:
345531, 37524025, 711170, 715700
Abstract:
In some embodiments, a video processing system including video processor, an external memory, and an integrated circuit that implements both a memory controller (having embedded intelligence) and an internal memory coupled to the memory controller. The memory controller is configured to pre-cache in the internal memory partial frames of reference video data in the external memory (e. g. , N-line slices of M-line reference frames, where M>N), and to respond to requests (e. g. , from the video processor) for blocks of reference video data including by determining whether each requested block (or each of at least two portions thereof) has been pre-cached in the internal memory, causing each requested cached block (or portion thereof) to be read from the internal memory, and causing each requested non-cached block (or portion thereof) to be read from the external memory. Preferably, the pre-caching is performed in a predetermined manner independent of which read requests for the reference data are actually asserted, and exploits known correlation between two-dimensional pixel locality of each block (“current block”) of data to undergo processing (e. g. , decoding) using reference data, two-dimensional pixel locality of each block of reference data that may be requested to process the current block, and probability that each such reference data block will be needed to process the current block.

Clock-Gated Series-Coupled Data Processing Modules

US Patent:
20090259862, Oct 15, 2009
Filed:
Apr 10, 2008
Appl. No.:
12/101082
Inventors:
Ravi Bulusu - San Jose CA, US
Shu-Jen Fang - Cupertino CA, US
Srivatsan Varadarajan - Campbell CA, US
Han Chou - Santa Clara CA, US
Sandro Pintz - Menlo Park CA, US
Aiyun Wang - San Jose CA, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G06F 1/32
US Classification:
713322
Abstract:
A clock module is coupled in parallel to a number of data processing modules that are coupled in series. The data processing modules can be individually clock-gated. Each of the data processing modules can determine whether or not it can be placed into an idle state. To reduce power consumption, any subset of the data processing modules that are eligible to be placed in an idle state can be clock-gated. The remaining data processing modules can continue to receive clock signals from the clock module and thus can continue to process data.

Technique For Reducing Bandwidth Consumption During Frame Rotation

US Patent:
20140347379, Nov 27, 2014
Filed:
May 24, 2013
Appl. No.:
13/902571
Inventors:
- Santa Clara CA, US
Han CHOU - Santa Clara CA, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G06T 1/60
G06T 3/60
US Classification:
345537
Abstract:
A decode engine is configured to perform a rotation operation with a macroblock in conjunction with performing a deblocking operation that involves the macroblock. The decode engine decodes the macroblock and performs the deblocking operation to generate a deblocked macroblock, then rotates the deblocked macroblock and writes the rotated, deblocked macroblock to memory. With this approach, multiple, redundant reads of the macroblock, as required with conventional rotation techniques, may be avoided.
Han B Chou from Santa Clara, CA, age ~49 Get Report