US Patent:
20130290795, Oct 31, 2013
Inventors:
Janusz Rajski - West Linn OR, US
Mark A. Kassab - Wilsonville OR, US
Grzegorz Mrugalski - Swardzez, PL
Nilanjan Mukherjee - Wilsonville OR, US
Jakub Janicki - Poznan, PL
Jerzy Tyszer - Poznan, PL
Avijit Dutta - Tigard OR, US
Assignee:
Mentor Graphics Corporation - Wilsonville OR
International Classification:
H04L 12/26
Abstract:
Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.
